| Patent Number |
Title Of Patent |
Date Issued |
| 7391226 |
Contact resistance test structure and methods of using same |
June 24, 2008 |
| The present invention is directed to a contact resistance test structure and methods of using same. In one illustrative embodiment, the method includes forming a test structure comprised of two gate electrode structures, forming a plurality of conductive contacts to a doped region be |
| 7355201 |
Test structure for measuring electrical and dimensional characteristics |
April 8, 2008 |
| A test structure includes first and second combs, at least a first pair of base nodes, and a second pair of finger nodes. The first comb includes a first base and a first plurality of fingers extending from the first base. The second comb includes a second base and a second plurality of |
| 6964875 |
Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitan |
November 15, 2005 |
| Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevent |
| 6867130 |
Enhanced silicidation of polysilicon gate electrodes |
March 15, 2005 |
| Semiconductor devices exhibiting reduced gate resistance and reduced silicide spiking in source/drain regions are fabricated by forming thin metal silicide layers on the gate electrode and source/drain regions and then selectively resilicidizing the gate electrodes. Embodiments include |
| 6841832 |
Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitan |
January 11, 2005 |
| Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevent |
| 6780776 |
Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop la |
August 24, 2004 |
| A method of forming a semiconductor device provides a gate electrode on a substrate and forms a polysilicon reoxidation layer over the substrate and the gate electrode. A nitride layer is deposited over the polysilicon reoxidation layer and anisotropically etched The etching stops on the |
| 6764917 |
SOI device with different silicon thicknesses |
July 20, 2004 |
| A method of manufacturing a semiconductor device includes providing a silicon semiconductor layer over an insulating layer, and partially removing a first portion of the silicon layer. The silicon layer includes the first portion and a second portion, and a thickness of the second po |
| 6713357 |
Method to reduce parasitic capacitance of MOS transistors |
March 30, 2004 |
| The present invention relates to a method for fabricating MOS transistors with reduced parasitic capacitance. The present invention is based upon recognition that the parasitic capacitance of MOS transistors, such as are utilized in the manufacture of CMOS and IC devices, can be reduced |
| 6661057 |
Tri-level segmented control transistor and fabrication method |
December 9, 2003 |
| A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. Afte |
| 6552776 |
Photolithographic system including light filter that compensates for lens error |
April 22, 2003 |
| A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error |
| 6410409 |
Implanted barrier layer for retarding upward diffusion of substrate dopant |
June 25, 2002 |
| Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron includes implanting nitrogen to form a nitrogen barrier layer near the upper boundary of t |
| 6380055 |
Dopant diffusion-retarding barrier region formed within polysilicon gate layer |
April 30, 2002 |
| A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separately formed layers of polysilico |
| 6376330 |
Dielectric having an air gap formed between closely spaced interconnect lines |
April 23, 2002 |
| A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary t |
| 6372588 |
Method of making an IGFET using solid phase diffusion to dope the gate, source and drain |
April 16, 2002 |
| A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating layer over the gate and the device |
| 6353253 |
Semiconductor isolation region bounded by a trench and covered with an oxide to improve planariz |
March 5, 2002 |
| An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend enti |
| 6326298 |
Substantially planar semiconductor topography using dielectrics and chemical mechanical polish |
December 4, 2001 |
| A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than tha |
| 6323095 |
Method for reducing junction capacitance using a halo implant photomask |
November 27, 2001 |
| A method for forming a semiconductor device is provided. The method includes providing a substrate having a gate formed thereon. A first doped region is formed in the substrate. The first doped region extends a first distance from the gate. A second doped region is formed in the substrat |
| 6261885 |
Method for forming integrated circuit gate conductors from dual layers of polysilicon |
July 17, 2001 |
| A method for fabricating an integrated circuit is presented wherein a first polysilicon layer dielectrically spaced above a semiconductor substrate is provided. The semiconductor substrate contains a first active region and a second active region. A first dopant is selectively introduced |
| 6259142 |
Multiple split gate semiconductor device and fabrication method |
July 10, 2001 |
| A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are electrically isolated from one another |
| 6225151 |
Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion |
May 1, 2001 |
| A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing step. The nitrogen liner may be |
| 6208015 |
Interlevel dielectric with air gaps to lessen capacitive coupling |
March 27, 2001 |
| A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source deposited on a first level interconnect to form air gaps at midpoints between adjacent |
| 6201278 |
Trench transistor with insulative spacers |
March 13, 2001 |
| An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacer |
| 6197645 |
Method of making an IGFET with elevated source/drain regions in close proximity to gate with slo |
March 6, 2001 |
| An IGFET with elevated source and drain regions in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a lower gate level over a semiconductor substrate, wherein the lower gate level includes a top surface, a bottom surface and |
| 6188233 |
Method for determining proximity effects on electrical characteristics of semiconductor devices |
February 13, 2001 |
| The present invention is directed to a method for determining changes in electrical characteristics of semiconductor devices due to the fabrication of the devices in proximity to other devices or structures. The method comprises fabricating a plurality of semiconductor devices configured |
| 6166354 |
System and apparatus for in situ monitoring and control of annealing in semiconductor fabricatio |
December 26, 2000 |
| An optical monitoring of electrical characteristics of devices in a semiconductor is performed during an anneal step to detect the time annealing is complete and activation occurs. A surface photovoltage measurement is made during annealing to monitor the charge state on the surface |
| 6153833 |
Integrated circuit having interconnect lines separated by a dielectric having a capping layer |
November 28, 2000 |
| An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above o |
| 6150721 |
Integrated circuit which uses a damascene process for producing staggered interconnect lines |
November 21, 2000 |
| An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to |
| 6146978 |
Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with so |
November 14, 2000 |
| An interlevel interconnect is formed in a window opened through an isolation layer and through an etch barrier to expose an electrode surface and an adjacent isolation barrier. The interlevel interconnect may be disposed on substantially all of a portion of the underlying electrode s |
| 6137145 |
Semiconductor topography including integrated circuit gate conductors incorporating dual layers |
October 24, 2000 |
| A semiconductor topography including integrated circuit gate conductors incorporating dual polysilicon layers is provided. The semiconductor topography includes a semiconductor substrate. A first gate conductor is arranged upon a first gate dielectric and above the semiconductor subs |
| 6127719 |
Subfield conductive layer and method of manufacture |
October 3, 2000 |
| A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried inte |
| 6127264 |
Integrated circuit having conductors of enhanced cross-sectional area |
October 3, 2000 |
| A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lowe |
| 6111260 |
Method and apparatus for in situ anneal during ion implant |
August 29, 2000 |
| During a semiconductor substrate ion implant process thermal energy is supplied to raise the temperature of the semiconductor wafer. The increased temperature of the semiconductor wafer during implantation acts to anneal the implanted impurities or dopants in the wafer, reducing impu |
| 6100146 |
Method of forming trench transistor with insulative spacers |
August 8, 2000 |
| An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacer |
| 6096639 |
Method of forming a local interconnect by conductive layer patterning |
August 1, 2000 |
| A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited witho |
| 6096616 |
Fabrication of a non-ldd graded p-channel mosfet |
August 1, 2000 |
| A transistor and transistor fabrication method are presented in which a graded junction is formed using a plurality of source/drain dopant implants. The implants are performed such that higher concentrations of dopant species are implanted at lower energies and lower dopant concentra |
| 6091149 |
Dissolvable dielectric method and structure |
July 18, 2000 |
| A fabrication process is provided that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of |
| 6090703 |
Method of forming an integrated circuit having conductors of enhanced cross-sectional area with |
July 18, 2000 |
| A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lowe |
| 6087706 |
Compact transistor structure with adjacent trench isolation and source/drain regions implanted v |
July 11, 2000 |
| A semiconductor integrated circuit with a transistor formed within an active area defined by side-walls of a shallow trench isolation region, and method of fabrication thereof, is described. A gate electrode is formed over a portion of the active area and LDD regions formed that are |
| 6080629 |
Ion implantation into a gate electrode layer using an implant profile displacement layer |
June 27, 2000 |
| A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially resi |
| 6074904 |
Method and structure for isolating semiconductor devices after transistor formation |
June 13, 2000 |
| A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes a first pair of source/drain regions on either side of a first channel region and a second pair of source/drain regions on either side of a second channel |
| 6060345 |
Method of making NMOS and PMOS devices with reduced masking steps |
May 9, 2000 |
| A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first a |
| 6054356 |
Transistor and process of making a transistor having an improved LDD masking material |
April 25, 2000 |
| A transistor is provided with a gradually increasing source and drain arsenic doping profile in a lateral direction from the gate conductor sidewall surfaces. The very smooth doping profile ensures small electric fields at the channel-drain interface for the benefit of reducing hot-c |
| 6049134 |
Mask generation technique for producing an integrated circuit with optimal metal interconnect la |
April 11, 2000 |
| A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distan |
| 6048785 |
Semiconductor fabrication method of combining a plurality of fields defined by a reticle image u |
April 11, 2000 |
| Each region of multiple regions on a semiconductor substrate is imaged in an exposure field defined by a reticle. The regions are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The regions are interconnect |
| 6043544 |
Semiconductor gate conductor with a substantially uniform doping profile having minimal suscepti |
March 28, 2000 |
| A semiconductor fabrication process is presented which optimizes the position of impurities within a gate conductor a the source/drain straddling the gate conductor. Optimal positioning is achieved by using separate implants of different energies depending upon whether the gate condu |
| 6031289 |
Integrated circuit which uses a recessed local conductor for producing staggered interconnect li |
February 29, 2000 |
| An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to |
| 6030752 |
Method of stitching segments defined by adjacent image patterns during the manufacture of a semi |
February 29, 2000 |
| A method of stitching segments defined by adjacent image patterns of a photolithographic system during the manufacture of a semiconductor device is disclosed. The method includes forming a material over a semiconductor substrate, projecting a first image pattern over the substrate that |
| 6027859 |
Semiconductor substrate having extended scribe line test structure and method of fabrication the |
February 22, 2000 |
| The present invention generally provides a semiconductor substrate having an extended test structure and a method of fabricating such a substrate. A method of forming an extended test structure on a semiconductor substrate, consistent with one embodiment of the invention, includes formin |
| 5998293 |
Multilevel interconnect structure of an integrated circuit having air gaps and pillars separatin |
December 7, 1999 |
| An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced f |
| 5976956 |
Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate for |
November 2, 1999 |
| Dopant atoms have coefficients of diffusion that vary due to implant damage. Damaged regions are selected and created by implanting silicon atoms into a silicon substrate prior to formation of a gate electrode. The silicon atoms act as a getter for attracting selected dopants that are |
