| Patent Number |
Title Of Patent |
Date Issued |
| 7362248 |
Temperature tamper detection circuit and method |
April 22, 2008 |
| A sensing circuit determines whether an integrated circuit is currently exposed to one of a relatively low or a relatively high temperature. A selection circuit selects a measured voltage across the base-emitter of a bipolar transistor if the sensing circuit indicates that the circuit is |
| 7327544 |
Battery protection device |
February 5, 2008 |
| A battery protection structure is described. The structure provides battery overcharging protection while allowing for minimal battery voltage drop during normal battery operation. One resistance element sets voltage drop during normal operation, and the sum of two resistance element |
| 7224600 |
Tamper memory cell |
May 29, 2007 |
| A circuit includes a volatile memory array and a logic circuit operable to detect a memory array tamper situation and generate at least one control signal responsive thereto. Circuitry associated with each of the individual cells within the volatile memory array responds to the at le |
| 7132767 |
Method and circuit for switchover between a primary and a secondary power source |
November 7, 2006 |
| An integrated circuit and method for providing a switchover from the primary power source to the secondary power source to prevent a volatile element from losing stored data. The integrated circuit includes a forced power source switchover circuit for detecting that the supply level of |
| 7064534 |
Regulator circuitry and method |
June 20, 2006 |
| A regulator circuit and method are disclosed for a system. The regulator circuit may include a compare circuit for comparing a first supply voltage to a predetermined voltage level and generating an enable signal based upon the comparison. A selectively enabled voltage regulator is a |
| 7012417 |
Voltage regulator with stress mode |
March 14, 2006 |
| An electronic device incorporates a primary function circuit and a voltage regulator that provides a regulated voltage signal to the primary function circuit. The voltage regulator is responsive to a stress-enable signal indicative of whether or not an external voltage supplied to the |
| 6990011 |
Memory circuit and method for corrupting stored data |
January 24, 2006 |
| A method and circuit are disclosed for an integrated circuit having one or more memory cells, each memory cell including first and second p-channel transistor and first and second n-channel transistors configured as cross-coupled logic inverters between first and second reference voltage |
| 6816400 |
Circuit and method for testing a ferroelectric memory device |
November 9, 2004 |
| A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the column lines, for selectively sensing voltage levels appearing on the column lines and providing externall |
| 6787938 |
Method and circuit for switchover between a primary and a secondary power source |
September 7, 2004 |
| An integrated circuit and method for providing a switchover from the primary power source to the secondary power source to prevent a volatile element from losing stored data. The integrated circuit includes a forced power source switchover circuit for detecting that the supply level of t |
| 6781916 |
Integrated volatile and non-volatile memory |
August 24, 2004 |
| A memory device having a first and a second memory section, the first and the second memory sections being coupled to bit lines. The second memory section may include at least one fuse. The first memory section includes a volatile memory and the second memory section includes a non-volat |
| 6754094 |
Circuit and method for testing a ferroelectric memory device |
June 22, 2004 |
| A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the bit lines, for selectively determining the voltage levels appearing on the bit lines based on a measur |
| 6750683 |
Power supply detection circuitry and method |
June 15, 2004 |
| A circuit and method are disclosed for monitoring the voltage level of an unregulated power supply. The circuit includes a voltage reference circuit for generating a first reference voltage signal and a trim circuit which generates a trimmed reference voltage signal based upon the first |
| 6731550 |
Redundancy circuit and method for semiconductor memory devices |
May 4, 2004 |
| A redundancy circuit and method are disclosed for replacing at least one defective memory cell in a memory device. The redundancy circuit may include redundant decode circuitry for selectively maintaining an address of a defective memory cell in the memory device, receiving the input |
| 6603338 |
Device and method for address input buffering |
August 5, 2003 |
| A substantially noise-free address input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates both a logical true and complement representation of an address input signal and includes timing circuitry to place the logical true and |
| 6594192 |
Integrated volatile and non-volatile memory |
July 15, 2003 |
| A memory device having a first and a second memory section, the first and the second memory sections being coupled to bit lines. The second memory section may include at least one fuse. The first memory section includes a volatile memory and the second memory section includes a non-volat |
| 6584007 |
Circuit and method for testing a ferroelectric memory device |
June 24, 2003 |
| A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the column lines, for selectively sensing voltage levels appearing on the column lines and providing externall |
| 6556057 |
Noise suppression circuitry and method |
April 29, 2003 |
| A circuit and method are disclosed for monitoring the voltage level of an electrical signal, such as an unregulated power supply. The circuit includes a comparator that compares the electrical to the voltage reference and generates an output having a value that is based upon the comp |
| 6496439 |
Content addressable memory (CAM) with battery back-up and low current, stand-by mode controller |
December 17, 2002 |
| A content addressable memory (CAM) includes a voltage power supply input and an enable input. An enable control circuit is connected to the enable input, and operates to compare an external voltage to an enable reference voltage. If the external voltage drops below the enable reference v |
| 6476669 |
Reference voltage adjustment |
November 5, 2002 |
| A reference voltage trim circuit includes a voltage follower receiving the reference voltage to be trimmed, with one or more resistive loads providing predefined voltage shifts serially connected between the output of the voltage follower and the output of the trim circuit. The voltage |
| 6456519 |
Circuit and method for asynchronously accessing a ferroelectric memory device |
September 24, 2002 |
| A circuit and method are disclosed for asynchronously accessing accessing a ferroelectric memory device. The ferroelectric memory device internally generates timing signals for latching a received address signal and driving the row lines of the device based upon transitions appearing on |
| 6359819 |
Circuit and method for performing a stress test on a ferroelectric memory device |
March 19, 2002 |
| A circuit and method for performing a stress test on a ferroelectric memory device. The memory device includes a memory cell array having a plurality of row lines, column lines and plate lines. The memory device further includes test circuitry for receiving at least one test control sign |
| 6347381 |
Test mode circuitry for electronic storage devices and the like |
February 12, 2002 |
| A detection circuit and a test mode circuit incorporating the detection circuit is disclosed. The detection circuit includes an N-channel transistor having a first source, a first gate, and a first drain, wherein the first drain is connected to a supply voltage. The detection circuit |
| 6297996 |
Test mode activation and data override |
October 2, 2001 |
| A memory device with a test mode control circuit for entering a test mode responsive to a high on the Vss pin or a low on the Vcc pin that supply power to the output pins during normal operation of the memory device. In test mode the wordlines and bitlines of the memory remain active fro |
| 6294939 |
Device and method for data input buffering |
September 25, 2001 |
| A substantially noise-free data input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates either a logical true or complement output signal representation of a data input signal and includes timing circuitry to delay an edge transit |
| 6281734 |
Reference voltage adjustment |
August 28, 2001 |
| A reference voltage trim circuit includes a voltage follower receiving the reference voltage to be trimmed, with one or more resistive loads providing predefined voltage shifts serially connected between the output of the voltage follower and the output of the trim circuit. The voltage |
| 6144594 |
Test mode activation and data override |
November 7, 2000 |
| A memory device with a test mode control circuit for entering a test mode responsive to a high on the Vss pin or a low on the Vcc pin that supply power to the output pins during normal operation of the memory device. In test mode the wordlines and bitlines of the memory remain active fro |
| 6081466 |
Stress test mode entry at power up for low/zero power memories |
June 27, 2000 |
| A low/zero power memory device includes a deselect mode of operation wherein row decoders, column decoders, write decoders, pre-coders, post-coders and like operational circuits of the memory device needed for wordline and column activation are disabled until such time as a memory de |
| 6072732 |
Self-timed write reset pulse generation |
June 6, 2000 |
| A memory, such as a static random access memory (SRAM), includes at least one memory cell. The bit lines for that memory cell are selectively connected to corresponding write bit lines through a column select pass transistor and a selectively blowable fuse. A reset circuit is connected |
| 6041000 |
Initialization for fuse control |
March 21, 2000 |
| A circuit and method are provided for generating an initializing signal to a master enable fuse circuit on a redundant line decoder. An initialization pulse may be applied to a master enable circuit having a master enable fuse. The master enable fuse may be coupled to a switched volt |
| 6037799 |
Circuit and method for selecting a signal |
March 14, 2000 |
| A multiplexing circuit includes a reference terminal, a plurality of multiplexing input terminals, and a buffer having an input terminal and an output terminal. The multiplexing circuit also includes a plurality of first elements that each have a programmable conductivity and that are |
| 6034917 |
Control circuit for terminating a memory access cycle in a memory block of an electronic storage |
March 7, 2000 |
| A control circuit for terminating a memory access cycle in a memory block having at least one memory cell is disclosed. The at least one memory cell has unique process characteristics. The control circuit includes a memory block activation circuit for generating a memory block activation |
| 6006339 |
Circuit and method for setting the time duration of a write to a memory cell |
December 21, 1999 |
| A circuit and method for varying the time of a write cycle. A variable timer circuit is provided coupled to a write simulation circuit. The write simulation circuit receives a signal from a start write sensing circuit indicating that data is being written to memory cells of the array. Th |
| 5898235 |
Integrated circuit with power dissipation control |
April 27, 1999 |
| An integrated circuit device such as an SRAM operating in a battery backup mode, or operating in a quiescent mode when deselected in the operation of a portable electronic device, includes a power dissipation control circuit that reduces the voltage on an internal power supply node so th |
| 5896336 |
Device and method for driving a conductive path with a signal |
April 20, 1999 |
| A signal driver receives an input signal and an enable signal, and generates an output signal from the input signal when the enable signal has an active state. When the enable signal has an inactive state, the signal driver draws substantially zero supply current regardless of the le |
| 5883838 |
Device and method for driving a conductive path with a signal |
March 16, 1999 |
| A signal driver receives an input signal and an enable signal, and generates an output signal from the input signal when the enable signal has an active state. When the enable signal has an inactive state, the signal driver draws substantially zero supply current regardless of the le |
| 5883008 |
Integrated circuit die suitable for wafer-level testing and method for forming the same |
March 16, 1999 |
| A semiconductor integrated-circuit die includes a substrate of semiconductor material that has an edge. A conductive layer is disposed on the substrate, and a first insulator layer is disposed between the said substrate and the conductive layer. A functional circuit is disposed in th |
| 5864696 |
Circuit and method for setting the time duration of a write to a memory cell |
January 26, 1999 |
| A circuit and method for varying the time of a write cycle. A variable timer circuit is provided coupled to a write simulation circuit. The write simulation circuit receives a signal from a start write sensing circuit indicating that data is being written to memory cells of the array. Th |
| 5861660 |
Integrated-circuit die suitable for wafer-level testing and method for forming the same |
January 19, 1999 |
| A semiconductor integrated-circuit die includes a substrate of semiconductor material that has an edge. A conductive layer is disposed on the substrate, and a first insulator layer is disposed between the said substrate and the conductive layer. A functional circuit is disposed in th |
| 5848018 |
Memory-row selector having a test function |
December 8, 1998 |
| A memory-row selector includes an address input terminal, a mode terminal, and even-row-select and odd-row-select terminals. While a test signal level occupies the mode terminal (ie., during a test mode), the selector places either an active level or an inactive level on both of the |
| 5845059 |
Data-input device for generating test signals on bit and bit-complement lines |
December 1, 1998 |
| A data input circuit is used in a memory device having an externally accessible data pin. The data input circuit includes first and second data output terminals and a test terminal that receives a test signal. A data converter is coupled to the first and second data output terminals and |
| 5841709 |
Memory having and method for testing redundant memory cells |
November 24, 1998 |
| A memory device includes an array of matrix memory cells that each correspond to a matrix location within the matrix array, an array of redundant memory cells that each correspond to a redundant location within the redundant array, and address and test circuitry. During a first test |
| 5828622 |
Clocked sense amplifier with wordline tracking |
October 27, 1998 |
| A memory device with a sense amplifier enable line having the same resistance and capacitance as a local wordline. The sense amplifier enable line is made out of the same material, has the same layout, and has the same load placed on as a local wordline, this will make the sense ampl |
| 5825691 |
Circuit and method for terminating a write to a memory cell |
October 20, 1998 |
| A start write sensing circuit for sensing a start of a write is coupled to a write simulation circuit. The write simulation circuit preferably includes a memory cell replicate to mimic the amount of time required for writing data to the memory cell. The state of the data stored in the |
| 5808960 |
Circuit and method for tracking the start of a write to a memory cell |
September 15, 1998 |
| A circuit and method for determining the exact time at which data begins to be written to a memory cell. A write sensing circuit is connected to a data input line. When data is presented on the data input line for writing to the memory cell, the write sensing circuit outputs a write star |
| 5808947 |
Integrated circuit that supports and method for wafer-level testing |
September 15, 1998 |
| An integrated circuit is formed on a die that is formed as a detachable part of a semiconductor wafer. The wafer includes both a wafer test-mode path that is operable to carry a wafer test-mode signal and a wafer power-supply path that is operable to carry a wafer power-supply signal. |
| 5805611 |
Method and apparatus for testing high-frequency integrated circuits using a lower-frequency test |
September 8, 1998 |
| The present invention is directed to a method and apparatus for testing integrated circuits using a tester with a frequency limitation lower than what is needed to fully test the integrated circuit. Clock signals, each lower than that needed to test an integrated circuit at speed, are |
| 5802004 |
Clocked sense amplifier with wordline tracking |
September 1, 1998 |
| A memory device with a sense amplifier enable line having the same resistance and capacitance as a local wordline. The sense amplifier enable line is made out of the same material, has the same layout, and has the same load placed on as a local wordline, this will make the sense ampl |
| 5793247 |
Constant current source with reduced sensitivity to supply voltage and process variation |
August 11, 1998 |
| A current source for generating a current that is relatively stable over variations in the power supply voltage and temperature, and over variations in process parameters is disclosed. The current source includes a bias circuit, for producing a compensating bias voltage, and a current |
| 5790462 |
Redundancy control |
August 4, 1998 |
| An integrated circuit memory structure is disclosed where the read and write buses (true and complement) are coupled to redundant input/output select circuits through permanently programmable selection element that can disconnect the read and write busses from the redundant input/output |
| 5771195 |
Circuit and method for replacing a defective memory cell with a redundant memory cell |
June 23, 1998 |
| A memory access circuit is provided for isolating a matrix memory cell from and coupling a redundant memory cell to a data line when the matrix memory cell is defective. The memory access circuit includes a matrix switch that is coupled between the matrix memory cell and the data line. W |
