| Patent Number |
Title Of Patent |
Date Issued |
| 7372142 |
Vertical conduction power electronic device package and corresponding assembling method |
May 13, 2008 |
| A vertical conduction power electronic device package and corresponding assembly method comprising at least a metal frame suitable to house at least a plate or first semiconductor die having at least a first and a second conduction terminal on respective opposed sides of the first die. |
| 7304335 |
Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and me |
December 4, 2007 |
| A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced |
| 7205607 |
Semiconductor power device with insulated gate and trench-gate structure and corresponding manuf |
April 17, 2007 |
| A semiconductor power device includes an insulated gate and a trench-gate structure. The trench-gate structure is formed on a semiconductor substrate covered by an epitaxial layer. The trench is formed in the semiconductor to form the device gate region. A dielectric coating is provi |
| 7126173 |
Method for enhancing the electric connection between a power electronic device and its package |
October 24, 2006 |
| An electronic power device of improved structure is fabricated with MOS technology to have a gate finger region and corresponding source regions on either sides of the gate region. This device has a first-level metal layer arranged to independently contact the gate region and source |
| 7091558 |
MOS power device with high integration density and manufacturing process thereof |
August 15, 2006 |
| A MOS power device having: a body; gate regions on top of the body and delimiting therebetween a window; a body region, extending in the body underneath the window; a source region, extending inside the body region throughout the width of the window; body contact regions, extending t |
| 7067363 |
Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and me |
June 27, 2006 |
| A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced |
| 6566690 |
Single feature size MOS technology power device |
May 20, 2003 |
| A MOS technology power device includes a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating |
| 6548864 |
High density MOS technology power device |
April 15, 2003 |
| A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulati |
| 6492691 |
High integration density MOS technology power device structure |
December 10, 2002 |
| High density MOS technology power device structure, including body regions of a first conductivity type formed in a semiconductor layer of a second conductivity type, wherein the body regions include at least one plurality of substantially rectilinear and substantially parallel body stri |
| 6468866 |
Single feature size MOS technology power device |
October 22, 2002 |
| A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulatin |
| 6404010 |
MOS technology power device |
June 11, 2002 |
| A MOS technology power device is described which comprises a plurality of elementary active units and a part of said power device which is placed between zones where the elementary active units are formed. The part of the power device comprises at least two heavily doped body regions of |
| 6326271 |
Asymmetric MOS technology power device |
December 4, 2001 |
| A MOS technology power device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type superimposed over the semiconductor substrate, an insulated gate layer covering the semiconductor layer, a plurality of substantially rectilinear elongated openings p |
| 6222232 |
Asymmetric MOS technology power device |
April 24, 2001 |
| A MOS technology power device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type superimposed over the semiconductor substrate, an insulated gate layer covering the semiconductor layer, a plurality of substantially rectilinear elongated openings p |
| 6064087 |
Single feature size MOS technology power device |
May 16, 2000 |
| A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulatin |
| 6054737 |
High density MOS technology power device |
April 25, 2000 |
| A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulati |
| 6040609 |
Process for integrating, in a single semiconductor chip, MOS technology devices with different t |
March 21, 2000 |
| Process for integrating in a same MOS technology devices with different threshold voltages. Simultaneously forming on a semiconductor material layer of at least two gate electrodes for at least two MOS devices, said gate electrodes comprising substantially rectilinear portions and corner |
| 6030870 |
High density MOS technology power device |
February 29, 2000 |
| A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulati |
| 5985721 |
Single feature size MOS technology power device |
November 16, 1999 |
| A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulatin |
| 5981998 |
Single feature size MOS technology power device |
November 9, 1999 |
| A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulatin |
| 5981343 |
Single feature size mos technology power device |
November 9, 1999 |
| A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulatin |
