| Patent Number |
Title Of Patent |
Date Issued |
| 7437139 |
Method and apparatus for calibrating filtering of a transceiver |
October 14, 2008 |
| A method and apparatus of calibrating filtering of receive and transmit signals is disclosed. The method of calibrating filtering of a received signal includes injecting an LO signal. The injected LO signal is filtered by a tunable filter. The filtered signal is frequency down-conver |
| 7138880 |
Turbo-charged relaxation oscillator method and apparatus |
November 21, 2006 |
| A method for producing an oscillating signal comprises: generating an oscillating signal by discharging after charging to a high trigger level and charging after discharging to a low trigger level; and turbo-charging at the initial of a change-over from charging to discharging while |
| 7038294 |
Planar spiral inductor structure with patterned microelectronic structure integral thereto |
May 2, 2006 |
| Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a spirally patterned conductor layer which terminates in a microelectronic structure within the center of the spirally patterned conductor layer. |
| 6881996 |
Metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect laye |
April 19, 2005 |
| A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (X.sub.c /R) and which does not require additional masks and metal layers. The meth |
| 6812088 |
Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits |
November 2, 2004 |
| This MIM structure provides metal capacitors with high figure of merit Q (X.sub.c /R) and does not require additional masks and metal layers. A copper capacitor bottom metal (CBM) electrode is formed, while concurrently forming the pad contacts and level of copper interconnections by |
| 6667217 |
Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process |
December 23, 2003 |
| A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step, used to form the opening in an |
| 6489816 |
Frequency converter with direct current suppression |
December 3, 2002 |
| A frequency converter circuit and method is disclosed. The circuit may comprise: two pairs of differential amplifying transistors; two current mirrors, wherein each of the two current mirrors is operable to feed a respective one of the two pairs of differential amplifying transistors; a |
| 6472721 |
Dual damascene interconnect structures that include radio frequency capacitors and inductors |
October 29, 2002 |
| In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both |
| 6444517 |
High Q inductor with Cu damascene via/trench etching simultaneous module |
September 3, 2002 |
| A new method is provided for the creation of an inductive over the surface of a semiconductor substrate. A first layer of metal is created in a layer of dielectric, a second layer of metal is created overlying the first layer of metal. The first layer of metal combined with the second la |
| 6404030 |
Chain gate MOS structure |
June 11, 2002 |
| A structure is disclosed for a multi-finger transistor with improved high frequency performance. An array of isolated active regions is formed in a semiconductor substrate. A source region and a drain region are formed in each of the active regions and are disposed on either side of a ce |
| 6366764 |
Wireless transmitter/receiver utilizing DSSS technology |
April 2, 2002 |
| A wireless LAN RF module uses parasitic element compensation devices in an antenna select circuit to improve port isolation. In addition, various combinations of RC filter networks and spurious radiation attenuators are incorporated into the Quad Demod/Mod and Synthesizer ;/circuits to p |
| 6329234 |
Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow |
December 11, 2001 |
| In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both |
| 6205171 |
Antenna selector switch |
March 20, 2001 |
| A wireless LAN RF module uses a low power transistor switchable voltage divider circuit to control the bias input of a GaAs MESFET output power amplifier. This bias control circuit provides stable, high speed on-off switching of the power amplifier stage by applying low power bias voltag |
| 5809188 |
Tunable optical filter or reflector |
September 15, 1998 |
| A tunable optical fiber filter or reflector is composed of a single-mode optical fiber having UV-induced fiber gratings in its core region. A planar surface is formed by a mechanical polishing technique such that the planar surface is contiguous to the core region of the optical fiber. T |
| 5781675 |
Method for preparing fiber-optic polarizer |
July 14, 1998 |
| A method for preparing a fiber-optic polarizer involves a first step in which the cladding layer of a single-mode optical fiber is side-polished to form a planar surface contiguous to the core region of the single-mode optical fiber. The planar surface is formed thereon a buffer diel |
