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Ching-Tien Ma Patents
Inventor:
Ma; Ching-Tien
Address:
Tainan, TW
No. of patents:
6
Patents:




Patent Number Title Of Patent Date Issued
6830877 Method for forming via and contact holes with deep UV photoresist December 14, 2004
A method for forming via openings or contact holes with improved aspect ratios by using a deep UV photoresist is described. In the method, after a deep UV photoresist layer is deposited on top of a thick oxide layer, the deep UV photoresist layer is pre-treated by a curing process with U
6764810 Method for dual-damascene formation using a via plug July 20, 2004
A method for improving a photolithographic patterning process in a dual damascene process including providing at least one via opening in a substrate including a low dielectric constant material; blanket depositing a photo-sensitive resinous layer to fill the at least one via opening;
6652666 Wet dip method for photoresist and polymer stripping without buffer treatment step November 25, 2003
A wet dip method for photoresist and polymer stripping from a wafer surface without the need for a buffer solvent treatment step is disclosed. In the method, the wafer is first exposed to an etchant solution that is maintained at a temperature of at least 80.degree. C. The wafer is then
6583062 Method of improving an aspect ratio while avoiding etch stop June 24, 2003
A plasma etching method for improving an aspect ratio including an etching profile including providing a substrate including an oxide containing insulating layer in a multilayer semiconductor device having at least a first underlying etching stop layer and at least a second etching stop
6570257 IMD film composition for dual damascene process May 27, 2003
The use of an intermetal dielectric (IMD) layer and an organic etch-stop layer are disclosed in forming a dual damascene in order to reduce the RC delay and the overall dielectric constant of the damascene interconnect. The disclosed IMD layer is an FSG and the etch-stop layer is an orga
6316351 Inter-metal dielectric film composition for dual damascene process November 13, 2001
The use of an intermetal dielectric (IMD) layer and an organic etch-stop layer are disclosed in forming a dual damascene in order to reduce the RC delay and the overall dielectric constant of the damascene interconnect. The disclosed IMD layer is an FSG and the etch-stop layer is an orga


 
 
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