| Patent Number |
Title Of Patent |
Date Issued |
| 7414258 |
Spacer electrode small pin phase change memory RAM and manufacturing method |
August 19, 2008 |
| A memory device comprising a first pan-shaped electrode having a side wall with a top side, a second pan-shaped electrode having a side wall with a top side and an insulating wall between the first side wall and the second side wall. The insulating wall has a thickness between the first |
| 7397060 |
Pipe shaped phase change memory |
July 8, 2008 |
| A memory cell device includes a bottom electrode, pipe shaped member comprising phase change material and a top electrode in contact with the pipe-shaped member. An electrically and thermally insulating material is inside the pipe-shaped member. An integrated circuit including an array |
| 7394088 |
Thermally contained/insulated phase change memory device and method (combined) |
July 1, 2008 |
| A memory device with improved heat transfer characteristics. The device first includes a dielectric material layer; first and second electrodes, vertically separated and having mutually opposed contact surfaces. A phase change memory element is encased within the dielectric material |
| 7388252 |
Two-bits per cell not-and-gate (NAND) nitride trap memory |
June 17, 2008 |
| A non-volatile memory array includes a semiconductor substrate having a main surface, a first source/drain region and a second source/drain region. The second source/drain region is spaced apart from the first source/drain region. A well region is disposed in a portion of the semicon |
| 7385235 |
Spacer chalcogenide memory device |
June 10, 2008 |
| The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings. |
| 7364935 |
Common word line edge contact phase-change memory |
April 29, 2008 |
| A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a first dimension of a bottom electrode and a second dimension controlled by an etch process. The contact area is |
| 7323732 |
MRAM array employing spin-filtering element connected by spin-hold element to MRAM cell structur |
January 29, 2008 |
| An MRAM array having enhanced magnetoresistance includes a spin filtering element connected by a spin hold element to the MRAM cell structures. A spin filtering element may serve several MRAM cell structures, by connecting the spin filtering element to a series of MRAM cell structures |
| 7321130 |
Thin film fuse phase change RAM and manufacturing method |
January 22, 2008 |
| A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first |
| 7314815 |
Manufacturing method of one-time programmable read only memory |
January 1, 2008 |
| An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. T |
| 7279380 |
Method of forming a chalcogenide memory cell having an ultrasmall cross-sectional area and a cha |
October 9, 2007 |
| A method of fabricating a chalcogenide memory cell is described. The cross-sectional area of a chalcogenide memory element within the cell is controlled by the thickness of a bottom electrode and the width of a word line. The method allows the formation of ultra small chalcogenide memory |
| 7251167 |
Method for programming multi-level nitride read-only memory cells |
July 31, 2007 |
| A method of programming data regions in a nitride read-only memory cell is described. In an erased state, the nitride read-only memory cell exhibits a low V.sub.t value. A data region that is to be programmed to a highest V.sub.t value is programmed first. Remaining data regions in the n |
| 7247511 |
Thin film phase-change memory |
July 24, 2007 |
| A memory cell comprises a chalcogenide random access memory (CRAM) cell and a CMOS circuit. The CMOS circuit accesses the CRAM cell. The CRAM cell has a cross-sectional area that is determined by a thin film process (e.g., a chalcogenide deposition thin film process) and by an iso-etchin |
| 7238994 |
Thin film plate phase change ram circuit and manufacturing method |
July 3, 2007 |
| A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Elect |
| 7220983 |
Self-aligned small contact phase-change memory method and device |
May 22, 2007 |
| The invention relates to a novel memory cell structure and process to fabricate chalcogenide phase change memory. More particularly, it produces a small cross-sectional area of a chalcogenide-electrode contact part of the phase change memory, which affects the current/power requireme |
| 7209389 |
Trap read only non-volatile memory (TROM) |
April 24, 2007 |
| A Trap Read Only Memory (TROM) architecture employs a NAND-type array structure configured as a read-only memory that is programmed only one time. The memory cells in the array comprise a gate terminal, a first channel terminal (source/drain), a second channel terminal (drain/source) |
| 7202493 |
Chalcogenide memory having a small active region |
April 10, 2007 |
| A chalcogenide phase change memory cell has a substrate with a conductor line. The conductor line has a contact end. An insulating layer is located over the substrate and conductor line. An aperture is located in the insulating layer. The aperture extends to the substrate. A memory m |
| 7196924 |
Method of multi-level cell FeRAM |
March 27, 2007 |
| Disclosed are use methods, integrated circuits, and manufacturing methods for ferroelectric memory. A data value from multiple data values is received, for example by a state machine controlling the ferroelectric memory. The different data values correspond to different particular du |
| 7158420 |
Inversion bit line, charge trapping non-volatile memory and method of operating same |
January 2, 2007 |
| A charge trapping memory device in which a field induced inversion layer is used to replace the source and drain implants. The memory cell are adapted to store two bits, one on the left side and one on the right side of the charge trapping structure. A positive threshold voltage erase |
| 7138687 |
Thin film phase-change memory |
November 21, 2006 |
| A memory cell comprises a chalcogenide random access memory (CRAM) cell and a CMOS circuit. The CMOS circuit accesses the CRAM cell. The CRAM cell has a cross-sectional area that is determined by a thin film process (e.g., a chalcogenide deposition thin film process) and by an iso-etchin |
| 7067865 |
High density chalcogenide memory cells |
June 27, 2006 |
| A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed against a side wall of the chalcogenide alloy structure, wherein at least one of the side w |
| 7053406 |
One-time programmable read only memory and manufacturing method thereof |
May 30, 2006 |
| An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. T |
| 7038928 |
Method of determining optimal voltages for operating two-side non-volatile memory and the operat |
May 2, 2006 |
| A method of determining an optimal reading voltage for reading a two-side non-volatile memory programmed with a threshold voltage Vt is described. A first side of a memory cell is programmed to Vt, and then an I.sub.1-Vg curve of the first side and an I.sub.2-Vg curve of the second side |
| 7038230 |
Horizontal chalcogenide element defined by a pad for use in solid-state memories |
May 2, 2006 |
| A process for fabricating phase-change elements having ultra small cross-sectional areas for use in phase change memory cells specifically and in semiconductor devices generally in which pads are implemented to create horizontally aligned phase change elements is disclosed. The eleme |
| 7033856 |
Spacer chalcogenide memory method |
April 25, 2006 |
| The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings. |
| 6984548 |
Method of making a nonvolatile memory programmable by a heat induced chemical reaction |
January 10, 2006 |
| A nonvolatile memory cell occupying a minimum chip area is provided with a cell structure that includes two or more base materials being programmable by a heat induced chemical reaction to form a layer or layers of alloy. The formation of alloy results in a change in resistance of th |
| 6965522 |
Tunneling diode magnetic junction memory |
November 15, 2005 |
| A tunneling diode magnetic junction memory that eliminates the need for a separate semiconductor diode is disclosed. The diode is formed by an insulating layer that is located between a free magnetic layer and a pinned magnetic layer. The present invention further discloses a method of |
| 6960801 |
High density single transistor ferroelectric non-volatile memory |
November 1, 2005 |
| A single transistor ferroelectric memory ("FEM") cell, useful for high density ferroelectric random access memory ("FRAM") applications, and a method for making the same, are herein disclosed. The FEM cell comprises a FEM gate unit having a top electrode, a ferroelectric material layer, |
| 6956774 |
Nonvolatile memory programmable by a heat induced chemical reaction |
October 18, 2005 |
| A nonvolatile memory cell occupying a minimum chip area including a cell structure that includes two or more base materials being programmable by a heat induced chemical reaction to form a layer or layers of alloy. The formation of alloy results in a change in resistance of the cell stru |
| 6952038 |
3D polysilicon ROM and method of fabrication thereof |
October 4, 2005 |
| A 3D polysilicon ROM including an isolated SiO.sub.2 layer on a silicon substrate, and an N+ polysilicon layer on the isolated SiO.sub.2 layer. The N+ polysilicon layer is further defined by a plurality of parallel, separate word lines. A first oxide layer fills the space between the wor |
| 6940757 |
Structure and operating method for nonvolatile memory cell |
September 6, 2005 |
| A structure and operating method for a nonvolatile memory cell. First and second bit lines are disposed on a substrate. A channel is disposed between the first and second bit lines in an active area. First and second selective gates are disposed on the first and second bit lines resp |
| 6927136 |
Non-volatile memory cell having metal nano-particles for trapping charges and fabrication thereo |
August 9, 2005 |
| A non-volatile memory cell is described. The non-volatile memory cell comprises a substrate, a charge-trapping layer, a gate and a source/drain. The charge-trapping layer comprises an insulating layer and metal nano-particles contained therein, wherein the metal nano-particles are fo |
| 6914282 |
Ferroelectric device and method for making |
July 5, 2005 |
| A ferroelectric subassembly for an integrated circuit includes a second layer lying between and in contact with first and third layers. The second layer comprises a ferroelectric material while the first and third layers comprise capacitor electrodes in contact with the second layer. At |
| 6894340 |
Non-volatile semiconductor memory cell utilizing poly-edge discharge |
May 17, 2005 |
| A process and structure for fabricating a non-volatile memory cell through the formation of a source and drain region and a charge trapping layer located therebetween is presented. E-fields for generating trapped charges are formed through using poly-edge discharge techniques wherein the |
| 6893912 |
Ferroelectric capacitor memory device fabrication method |
May 17, 2005 |
| A ferroelectic capacitor memory device is fabricated by a forming a substrate including integrated circuitry with an interconnect layer and pass transistors. First capacitor electrodes, contacts and pads are simultaneously formed on the substrate and are connected to an associated pa |
| 6873541 |
Nonvolatile memory programmble by a heat induced chemical reaction |
March 29, 2005 |
| A nonvolatile memory cell occupying a minimum chip area is provided with a cell structure that includes two or more base materials being programmable by a heat induced chemical reaction to form a layer or layers of alloy. The formation of alloy results in a change in resistance of the ce |
| 6864503 |
Spacer chalcogenide memory method and device |
March 8, 2005 |
| The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings. |
| 6838692 |
Chalcogenide memory device with multiple bits per cell |
January 4, 2005 |
| A memory device with multiple bits per-cell. The memory device includes a side electrode; a doped semiconductor region disposed laterally in contact with a sidewall of the side electrode, such that the doped semiconductor region forms a diode, or the junction between the side electrode a |
| 6830952 |
Spacer chalcogenide memory method and device |
December 14, 2004 |
| The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings. |
| 6828081 |
Method and system for lithography using phase-change material |
December 7, 2004 |
| Methods and systems are provided for forming an electrical interconnect layer between two layers of an integrated circuit. The interconnect layer is formed using a material having a first electrical conductivity corresponding to a first state and a second electrical conductivity corr |
| 6750101 |
Method of manufacturing self-aligned, programmable phase change memory |
June 15, 2004 |
| A self-aligned, nonvolatile memory structure based upon phase change materials, including chalcogenides, can be made with a very small area on an integrated circuit. The manufacturing process results in self-aligned memory cells requiring only two array-related masks defining the bit lin |
| 6587368 |
Non-volatile memory circuit |
July 1, 2003 |
| A memory circuit has a volatile memory portion and two ferroelectric capacitors. The volatile memory portion has two internal nodes and the ferroelectric capacitors are coupled in series to form a common node and two extreme poles. One of the two internal nodes is connected to the co |
| 6579760 |
Self-aligned, programmable phase change memory |
June 17, 2003 |
| A self-aligned, nonvolatile memory structure based upon phase change materials, including chalcogenides, can be made with a very small area on an integrated circuit. The manufacturing process results in self-aligned memory cells requiring only two array-related masks defining the bit lin |
| 6576479 |
Method for forming vertical ferroelectric capacitor comprising forming ferroelectric material in |
June 10, 2003 |
| A vertical ferroelectric capacitor structure and the method of fabricating the same. An insulating layer is formed on a semiconductor substrate. A lower opening and an upper opening with the depth larger than the width are defined and formed in the insulating layer. A conductive material |
| 6574134 |
Non-volatile ferroelectric capacitor memory circuit having nondestructive read capability |
June 3, 2003 |
| A non-destructive ferroelectric capacitor-based memory circuit has a plurality of word lines located in parallel to each other. A plurality of bit lines is located across the word lines and a plurality of memory cells is located at intersections between the word lines and the bit lines. |
| 6512687 |
Non-volatile ferroelectric capacitor memory circuit |
January 28, 2003 |
| A non-volatile memory circuit having ferroelectric capacitors. Two ferroelectric capacitors are combined with a volatile memory cell. The volatile memory cell has two internal nodes. The two internal nodes are respectively connected to the two ferroelectric capacitors. The ferroelect |
| 6388913 |
Method for detecting polarization of a ferroelectric capacitor in a ferroelectric memory and the |
May 14, 2002 |
| A method for detecting polarization of a ferroelectric capacitor in a ferroelectric memory and thereof structure is provided by detecting polarization of a ferroelectric capacitor through a characteristic which present different voltage values by providing different voltages on the f |
| 6385077 |
Non-volatile memory cell and sensing method |
May 7, 2002 |
| A non-volatile ferroelectric capacitor memory of the present invention comprises a plurality of word lines located in parallel to each other, a plurality of bit lines across the word lines, a plurality of sensing ferroelectric capacitor connected to ground, a plurality of output tran |
| 6285586 |
Nonvolatile static random access memory |
September 4, 2001 |
| A nonvolatile static random access memory adapted for a semiconductor substrate mainly comprises a nonvolatile erasable programmable memory transistor having a charge storage layer for storing data charges, and further having a first gate terminal, a first source terminal, and a first |
| 6282118 |
Nonvolatile semiconductor memory device |
August 28, 2001 |
| A nonvolatile semiconductor memory device adapted for a semiconductor substrate includes a Dynamic Random Access Memory (DRAM) cell and a nonvolatile erasable programmable (NEP) transistor. The DRAM cell includes a control transistor having a first gate connected to a first word line, a |
