| Patent Number |
Title Of Patent |
Date Issued |
| 7413996 |
High k gate insulator removal |
August 19, 2008 |
| A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k |
| 7405116 |
Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow |
July 29, 2008 |
| A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals use |
| 7365015 |
Damascene replacement metal gate process with controlled gate profile and length using Si.sub.1- |
April 29, 2008 |
| A method of forming a metal gate in a wafer. PolySi.sub.1-xGe.sub.x and polysilicon are used to form a tapered groove. Gate oxide, PolySi.sub.1-xGe.sub.x, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi.sub.1-xGe.sub.x, and ga |
| 7341978 |
Superconductor wires for back end interconnects |
March 11, 2008 |
| An improvement to an integrated circuit, of electrically conductive interconnects formed of a superconducting material. In this manner, the electrically conductive interconnects can be made very small, and yet still have adequate conductively. In various embodiments, all of the elect |
| 7312127 |
Incorporating dopants to enhance the dielectric properties of metal silicates |
December 25, 2007 |
| The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodi |
| 7259462 |
Interconnect dielectric tuning |
August 21, 2007 |
| An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the |
| 7081406 |
Interconnect dielectric tuning |
July 25, 2006 |
| An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the |
| 7064062 |
Incorporating dopants to enhance the dielectric properties of metal silicates |
June 20, 2006 |
| The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodi |
| 6864141 |
Method of incorporating nitrogen into metal silicate based dielectrics by energized nitrogen ion |
March 8, 2005 |
| A method of making a thin gate dielectric includes providing a metal silicate on a silicon substrate. Nitrogen is implanted into the metal silicate. |
| 6849512 |
Thin gate dielectric for a CMOS transistor and method of fabrication thereof |
February 1, 2005 |
| A method of making a thin gate dielectric includes implanting a barrier substance into a region of a silicon substrate. A capacitance-increasing material is implanted into the silicon substrate. An outside layer of the silicon substrate is oxidized to form a first silicon oxide layer. Th |
| 6830943 |
Thin film CMOS calibration standard having protective cover layer |
December 14, 2004 |
| Embodiments of the invention include a calibration standard for semiconductor metrology tools. The standard comprises a substrate having a surface with a calibration layer formed thereon. A protective layer is formed over the underlying calibration layer. The calibration layer and pr |
| 6818516 |
Selective high k dielectrics removal |
November 16, 2004 |
| A method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode layer is the patterned. LDD regions are formed using an ion implantation process, ther |
| 6746925 |
High-k dielectric bird's beak optimizations using in-situ O2 plasma oxidation |
June 8, 2004 |
| In a method of forming an integrated circuit device, sidewall oxides are formed by plasma oxidation on the patterned gate. This controls encroachment beneath a dielectric layer underlying the patterned gate. The patterned gate is oxidized using in-situ O.sub.2 plasma oxidation. The p |
| 6674092 |
Thin film CMOS calibration standard having protective cover layer |
January 6, 2004 |
| Embodiments of the invention include a calibration standard for semiconductor metrology tools. The standard comprises a substrate having a surface with a calibration layer formed thereon. A protective layer is formed over the underlying calibration layer. The calibration layer and pr |
| 6606450 |
Method and apparatus for processing video signals having associated access restriction data |
August 12, 2003 |
| A method and apparatus that includes processing for restricting usage of video signals in accordance with associated access restriction data begins by detecting the presence of the associated access restriction data as video signals are being received. The processing continues by interpr |
