| Patent Number |
Title Of Patent |
Date Issued |
| 6921629 |
Self-aligned fabrication process for a nozzle plate of an inkjet print head |
July 26, 2005 |
| A self-aligned fabrication process for a nozzle plate of an inkjet print head. A substrate is provided with an activated device and a first film is formed on the substrate. Then, a second film is formed on the first film. Next, the second film is defined to form a convex portion correspo |
| 6773094 |
Method of using photolithography and etching for forming a nozzle plate of an inkjet print head |
August 10, 2004 |
| A method of forming a nozzle plate of an inkjet print head. A silicon chip is provided with an activated device and a first film is formed on the silicon chip, with a first opening corresponding to the activated device. Then, a second film is formed on the first film. Next, a photoresist |
| 6569760 |
Method to prevent poison via |
May 27, 2003 |
| A method for fabricating a via openings, comprising the following steps. A semiconductor structure is provided. A low-k layer is formed upon the semiconductor structure. A via opening is formed within the low-k layer. An inert polymer liner layer is formed upon the low-k layer and within |
| 6479401 |
Method of forming a dual-layer anti-reflective coating |
November 12, 2002 |
| A method of forming an anti-reflective coating is described. A film is formed on a substrate. A first layer of an anti-reflective coating layer Is deposited on the film by chemical vapor deposition using a canrier gas, an organic halide gas and a hydrogen halide gas as gas sources. A sec |
| 6348707 |
Method of manufacturing semiconductor capacitor |
February 19, 2002 |
| A method of manufacturing dynamic random access memory (DRAM) capacitor. A semiconductor substrate having an insulation layer thereon is supplied. A triblock copolymer layer is formed over the insulation layer by performing a spin-coating process. The triblock copolymer layer is patterne |
| 6303431 |
Method of fabricating bit lines |
October 16, 2001 |
| A method of fabricating bit lines is described. A semiconductor substrate has isolation structures formed therein. Gate structures are formed over the semiconductor substrate. Each gate structure comprises a conducting gate layer and a cap layer on the conducting gate layer. A common sou |
| 6300240 |
Method for forming bottom anti-reflective coating (BARC) |
October 9, 2001 |
| A method for forming organic anti-reflective coating (ARC) is disclosed in the present invention. A substrate is provided and an ARC is deposited on the substrate using reactive gas. The reactive gas comprising compound gas containing carbon atom, hydrogen atom and halogen atom, where sa |
| 6287957 |
Self-aligned contact process |
September 11, 2001 |
| The present invention discloses a method for forming a self-aligned contact hole, which provides a large process window and ensures full utilization of bottom contact area even when the overlay is not well aligned. The method comprises the steps of (a) providing a semiconductor substrate |
| 6263586 |
Device and method for planarizing a thin film |
July 24, 2001 |
| A device and method for planarizing a film layer device on a silicon wafer. The device has a circular track whose surface faces the track center, a carrier capable of moving along the track and carrying wafers around with their front surfaces facing the center, and a set of heating eleme |
| 6180483 |
Structure and fabrication method for multiple crown capacitor |
January 30, 2001 |
| A multiple crown capacitor and a method of fabricating such a capacitor is described. The method is applicable to a substrate in which an isolation layer is formed on the substrate, with a node contact plug formed in the isolation layer. A sacrificial layer is then formed on the substrat |
| 6165909 |
Method for fabricating capacitor |
December 26, 2000 |
| A method for fabricating a capacitor is described. A dielectric layer and a polysilicon layer thereon are provided. A patterned oxide layer and spacers on the sidewalls of the patterned oxide layer are formed. The polysilicon layer is etched using the oxide layer and spacer as an etching |
| 6136646 |
Method for manufacturing DRAM capacitor |
October 24, 2000 |
| A method for manufacturing dynamic random access memory (DRAM) capacitor. A first insulation layer having a plurality of first plugs and second plugs therein is formed over a substrate. A plurality of bit lines is formed over the first insulation layer. Each bit line has a multiple of bi |
| 6133085 |
Method for making a DRAM capacitor using a rotated photolithography mask |
October 17, 2000 |
| A method of forming a bottom storage node of a DRAM capacitor over a contact plug is disclosed. The method comprises the steps of: depositing an oxide layer over the contact plug; etching the oxide layer using a first photoresist layer having with a first masking pattern, the first m |
| 6121082 |
Method of fabricating DRAM with novel landing pad process |
September 19, 2000 |
| A method for fabricating landing pads for DRAM cells is disclosed. The method comprises following steps: At first, a substrate formed with isolation regions, periphery transistor region and a defined DRAM region are patterned so that an oxide layer on the defined DRAM region are remo |
| 6110837 |
Method for forming a hard mask of half critical dimension |
August 29, 2000 |
| The present invention discloses a method for forming hard mask of half critical dimension on a substrate. A substrate is provided for the base of integrated circuits. A silicon oxide layer is formed on the substrate. A photoresist layer is formed on the silicon oxide layer and it is has |
| 6100577 |
Contact process using Y-contact etching |
August 8, 2000 |
| A method is disclosed for forming Y-shaped holes in semiconductor substrates by using Y-contact etching. The hole is formed with a single, two-step dry-etching process in a single chamber with one masking step for the whole hole. The upper portion of the Y-shaped hole is formed by means |
| 6096653 |
Method for fabricating conducting lines with a high topography height |
August 1, 2000 |
| A method for forming a metal interconnect structure over a high topography dielectric is disclosed. The method comprises the steps of: depositing a conductive layer over the high topography dielectric layer; depositing a planarized oxide layer over the conducting layer, patterning and et |
| 6037217 |
Method of fabricating a capacitor electrode structure in a dynamic random-access memory device |
March 14, 2000 |
| An integrated circuit (IC) fabrication method is provided for the fabrication of an electrode structure having an increased surface area for a double-crown type of capacitor in a dynamic random-access memory (DRAM) device. In this method, damascene technology is used, which can help |
| 6033966 |
Method for making an 8-shaped storage node DRAM cell |
March 7, 2000 |
| A method for manufacturing an 8-shaped bottom storage node. A dielectric layer and a polysilicon layer are deposited. A bit line contact and a storage node contact are formed through the dielectric layer and the polysilicon layer down to an access transistor. After formation of the bit |
| 6022776 |
Method of using silicon oxynitride to improve fabricating of DRAM contacts and landing pads |
February 8, 2000 |
| A method for forming a DRAM cell of a DRAM circuit is disclosed. The DRAM circuit includes a periphery region and a cell region. The DRAM cell is in the cell region and comprises an access transistor and a capacitor. The access transistor has a gate, a source, and a drain. The periphery |
| 5950104 |
Contact process using Y-contact etching |
September 7, 1999 |
| A method is disclosed for forming Y-shaped holes in semiconductor substrates by using Y-contact etching. The hole is formed with a single, two-step dry-etching process in a single chamber with one masking step for the whole hole. The upper portion of the Y-shaped hole is formed by means |
| 5924000 |
Method for forming residue free patterned polysilicon layer containing integrated circuit struct |
July 13, 1999 |
| A method for forming a patterned polysilicon layer employed within an integrated circuit structure. There is first provided a semiconductor substrate having formed thereupon a topographic substrate layer. There is then formed over the semiconductor substrate including the topographic |
| 5902133 |
Method of forming a narrow polysilicon gate with i-line lithography |
May 11, 1999 |
| A new method for forming a feature having a feature size of one half the resolution of the photolithography process by adjusting the etching conditions is achieved. A capping oxide layer is deposited overlying the feature layer. A first layer of photoresist is patterned using a photo |
| 5866478 |
Metallization process using artificial gravity |
February 2, 1999 |
| Voids in via holes in integrated circuits have been effectively removed by heating the vias to a relatively low temperature and then subjecting the entire structure (including the vias) to artificial gravitational forces. Said forces may be steadily applied, as in centrifuging, or they m |
| 5865891 |
Planarization process using artificial gravity |
February 2, 1999 |
| The time needed to planarize the surface of an integrated circuit is reduced by causing the planarization liquid to settle in the presence of artificial gravity that supplements natural gravity. A number of different ways to achieve artificial gravity are described. These include cen |
| 5773199 |
Method for controlling linewidth by etching bottom anti-reflective coating |
June 30, 1998 |
| A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket target layer. There is then formed upon the blanket target layer a blanket focusing layer formed from an organic anti-reflective coating (ARC) ma |
| 5688713 |
Method of manufacturing a DRAM cell having a double-crown capacitor using polysilicon and nitrid |
November 18, 1997 |
| A method for manufacturing an array of double-crown-shaped storage capacitors with increased capacitance on a dynamic random access memory (DRAM) device has been achieved. The invention utilizes a polysilicon and silicon nitride spacer to form the double-crown capacitors while forming |
