| Patent Number |
Title Of Patent |
Date Issued |
| 6958283 |
Method for fabricating trench isolation |
October 25, 2005 |
| A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The fir |
| 6897108 |
Process for planarizing array top oxide in vertical MOSFET DRAM arrays |
May 24, 2005 |
| The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP |
| 6821872 |
Method of making a bit line contact device |
November 23, 2004 |
| A method for making a bit line contact on a substrate is provided. Two gate conductor stacks are formed on a main surface of the substrate in close proximity to each other. A bit line contact forming area is defined above the area between the two gate conductor stacks. A silicon dioxide |
| 6794266 |
Method for forming a trench isolation structure |
September 21, 2004 |
| A method for forming a trench isolation structure. First, a substrate having at least one trench is provided. The trench is filled with a spin on glass (SOG) layer. Subsequently, a baking is performed on the SOG layer. The SOG layer is etched back to a predetermined depth. Next, a cu |
| 6770563 |
Process of forming a bottle-shaped trench |
August 3, 2004 |
| A process of forming a bottle-shaped trench. A semiconductor substrate with a trench is provided, on which a pad layer and hard mask layer are sequentially formed. A dielectric layer is formed on the hard mask layer to fill the trench. Part of the dielectric layer is etched to expose the |
