| Patent Number |
Title Of Patent |
Date Issued |
| D442175 |
Case for a personal computer |
May 15, 2001 |
|
| D359033 |
Portable computer |
June 6, 1995 |
|
| D346588 |
Computer |
May 3, 1994 |
|
| D346371 |
Display for computer |
April 26, 1994 |
|
| D346161 |
Keyboard for a computer |
April 19, 1994 |
|
| 7415393 |
Reliability buffering technique applied to a project planning model |
August 19, 2008 |
| A reliability buffering technique applies a reliability time buffer to a project planning model having activities. The reliability time buffer is placed before an associated downstream activity to provide a buffered downstream activity. The reliability buffer is provided having a time |
| 7409031 |
Data sampling method and apparatus with alternating edge sampling phase detection for loop chara |
August 5, 2008 |
| A method and apparatus for 2.times. oversampling of data having jitter. In some embodiments, the invention is a clock and data recovery device including an alternating edge sampling binary phase detector, and which is configured to stabilize loop characteristics in various jitter env |
| 7395494 |
Apparatus for encoding and decoding of low-density parity-check codes, and method thereof |
July 1, 2008 |
| An LDPC code encoding apparatus includes: a code matrix generator for generating and transmitting a parity-check matrix comprising a combination of square matrices having a unique value on each row and column thereof; an encoding means encoding block LDPC codes according to the parit |
| 7393410 |
Method of manufacturing nano-wire |
July 1, 2008 |
| There is provided a method of manufacturing a nano-wire using a crystal structure. In the method of manufacturing a nano-wire, a crystal grain having a plurality of crystal faces is used as a seed, and a crystal growing material having a lattice constant difference within a predeterm |
| 7378320 |
Method of forming asymmetric MOS transistor with a channel stopping region and a trench-type gat |
May 27, 2008 |
| A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a t |
| 7372927 |
Digital filter for software-defined radio system, digital intermediate frequency signal processi |
May 13, 2008 |
| Disclosed is a receiver digital filter for a digital IF signal processor suitable for the specification of each communication standard in a communication system that supports at least one communication standard. The filter for each standard is constructed as one block, and includes a |
| 7349863 |
Dynamic planning method and system |
March 25, 2008 |
| A dynamic planning method (DPM) generates a DPM project planning model. The DPM project planning model provides an activity pre-structured process model for activities of a DPM project plan. The DPM project planning model also provides a relationship pre-structured model for activity |
| 7315598 |
Data recovery using data eye tracking |
January 1, 2008 |
| A data recovery system for a serial digital data link includes a data sampler, compare logic, a phase controller, and a phase shifter. The data sampler samples input data three times in a bit time which time is determined by clock pulses generated by the phase shifter, and recovers d |
| 7301885 |
Laser diode driving circuit and laser diode controlling apparatus including the laser diode driv |
November 27, 2007 |
| A laser diode driving circuit and a laser diode controlling apparatus including the laser diode driving circuit. The laser diode driving circuit includes a voltage drop prevention unit, which prevents a voltage at an input terminal of the laser diode driving circuit from dropping to |
| 7300845 |
Method of manufacturing recess type MOS transistor having a dual diode impurity layer structure |
November 27, 2007 |
| The method of manufacturing a recess type MOS transistor improves a refresh characteristic. In the method, a channel impurity region is formed by ion implanting a first conductive impurity in an active region of a semiconductor substrate. Thereon, a second conductive impurity and the |
| 7260161 |
Hybrid multi-user interference cancellation method and device using clustering algorithm based o |
August 21, 2007 |
| Disclosed is a hybrid multi-user interference cancellation method for canceling interference between a plurality of user signals, which comprises: receiving a plurality of external user signals, calculating powers of the user signals, and numbering the calculated signal powers in the |
| 7178081 |
Simplified message-passing decoder for low-density parity-check codes |
February 13, 2007 |
| Disclosed is an implementation method for simplifying a complicated message-passing function in a decoder for decoding block codes encoded with low-density parity-check (LDPC) codes and only using a summator and a shifter to simplify the hardware structure of the decoder, in which me |
| 7145763 |
High-voltage electric double layer capacitor |
December 5, 2006 |
| The present invention relates to a high-voltage electric double layer capacitor (EDLC), and more particularly, to an EDLC in which a surge voltage and an operating voltage are enhanced by improving the structure of a unit cell. The EDLC according to the present invention includes a u |
| 7123887 |
Adaptive transmission and receiving method and device in wireless communication system with mult |
October 17, 2006 |
| Disclosed is an adaptive transmit and receive method and device in a multiple-antenna wireless communication system. A transmit mode comprises different main transmit modes each of which includes one or both of a sub-transmit mode based on STBC and a sub-transmit mode based on SM. A |
| 7102446 |
Phase lock loop with coarse control loop having frequency lock detector and device including sam |
September 5, 2006 |
| A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling t |
| 7093189 |
Method and device for performing soft decision decoding on Reed-Muller codes using decision by m |
August 15, 2006 |
| An RM code soft decision decoding method using decision by majority comprises: (a) performing multiplication on a bit group of a codeword, and calculating an information bit's estimate group; (b) summating elements of the group and obtaining a final estimate of the degree's informati |
| 6838341 |
Method for fabricating semiconductor device with self-aligned storage node |
January 4, 2005 |
| A method for fabricating a semiconductor device includes preparing a semiconductor substrate having a contact pad; forming a first insulating film having a storage node contact exposing the contact pad and having a stack structure of an upper interlayer insulating film, a bottom inte |
| 6692112 |
Monolithic ink-jet printhead |
February 17, 2004 |
| A monolithic ink-jet printhead, and a method for manufacturing the same, wherein the monolithic ink-jet printhead includes a manifold for supplying ink, an ink chamber having a hemispheric shape, and an ink channel formed monolithically on a substrate; a silicon oxide layer, in which a n |
| 6627575 |
Double metal cyanide complex catalyst for producing polyol |
September 30, 2003 |
| A double metal cyanide complex catalyst for producing polyol, which is produced by using monovalent alcohol and polyvalent alcohol as a complexing agent. The double metal cyanide complex catalyst has advantages in that when polyol is produced by an epoxide polymerization reaction, the |
| 6509699 |
Digital controlled electronic ballast with piezoelectric transformer |
January 21, 2003 |
| A digitally controlled electronic ballast with a piezoelectric transformer automatically controls the brightness of a lamp in a digital frequency modulation manner. The ballast power a rectifier for rectifying an input low-frequency AC voltage to obtain a DC voltage, a power factor impro |
| 6473664 |
Manufacturing process automation system using a file server and its control method |
October 29, 2002 |
| In an automation system, a plurality of machines are connected to a file server via a network and the job result data produced by the machines, are shared by the file server. The job result data processed from a machine (for example, a tester) are stored in the file server. Another machi |
| 6215149 |
Trenched gate semiconductor device |
April 10, 2001 |
| A semiconductor device having a trench type gate and a fabrication method therefor is provided. The semiconductor device includes a trench formed in a semiconductor substrate and a gate insulating layer formed on the inner walls of the trench. A gate fills the trench and is insulated fro |
| 5949103 |
MOSFET with tunneling insulation and fabrication method thereof |
September 7, 1999 |
| A tunneling insulation film MOSFET and a fabrication method for a tunneling insulation film MOSFET avoid a short channel effect and prevent a punchthrough phenomenon by forming a tunneling insulation film between a channel area and one of source area and a drain area. The fabrication |
| 5940336 |
Reference clock generating circuit in memory to be asynchronously precharged and activated |
August 17, 1999 |
| A reference clock generating circuit and method, the circuit having an OR unit for ORing signals, from plural address change defectors, indicative of a change in an inputted address to provide an OR-result on a common terminal; a delay unit for delaying the signals on the common terminal |
| 5883846 |
Latch type sense amplifier having a negative feedback device |
March 16, 1999 |
| A latch type sense amplifier having negative feedback means for use in a memory device includes a first switching unit which is turned on/off by an enable signal and initializes a system operation at a turn-on operation; a second switching unit which is turned on/off according to the vol |
| 5825693 |
Write control circuit for semiconductor memory |
October 20, 1998 |
| A write control circuit for a semiconductor memory that performs a high speed operations determines a write timing of data based on a control signal in cooperation with the logical combination of a write control signal and an equalization signal. The write control circuit further sta |
| 5708607 |
Data read circuit of a memory |
January 13, 1998 |
| A data read circuit of a memory includes an inverting unit, a precharging unit, a first amplifying unit, a second amplifying unit, and an output buffer unit. The inverting unit inverts data from a sense amplifier, and the precharging unit precharges a data bus line to Vcc/2. The first |
| 5654927 |
Data transmission apparatus for a memory |
August 5, 1997 |
| A data transmission apparatus for a memory comprises precharging means for precharging a data bus, the precharging means being enabled by a first control signal outputted from a first externally connected element before data is transmitted to the data bus; a first inverter for inverting |
