| Patent Number |
Title Of Patent |
Date Issued |
| 7202142 |
Method for producing low defect density strained -Si channel MOSFETS |
April 10, 2007 |
| A silicon strained channel MOSFET device and method for forming the same the method providing improved wafer throughput and low defect density including the steps of providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected |
| 7012009 |
Method for improving the electrical continuity for a silicon-germanium film across a silicon/oxi |
March 14, 2006 |
| A method for making an improved silicon-germanium layer on a substrate for the base of a heterojunction bipolar transistor is achieved using a two-temperature process. The method involves growing a seed layer at a higher temperature to reduce the grain size with shorter reaction times, |
| 6982208 |
Method for producing high throughput strained-Si channel MOSFETS |
January 3, 2006 |
| A method for forming a strained silicon layer device with improved wafer throughput and low defect density including providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane and tri |
| 6936530 |
Deposition method for Si-Ge epi layer on different intermediate substrates |
August 30, 2005 |
| A method of forming an Si--Ge epitaxial layer comprising the following steps. A structure is provided and a doped Si--Ge seed layer is formed thereover. The doped Si--Ge seed layer having increased nucleation sites. A Si--Ge epitaxial layer upon the doped Si--Ge seed layer whereby the |
| 6911369 |
Discontinuity prevention for SiGe deposition |
June 28, 2005 |
| The present disclosure provides a process for producing a SiGe layer in a bipolar device having a reduced amount of gaps or discontinuities on a shallow trench isolation (STI) region use for a base electrode connection. The process is used for forming an SiGe layer for use in a semicondu |
| 6734101 |
Solution to the problem of copper hillocks |
May 11, 2004 |
| A new method of reducing copper hillocks in copper metallization is described. An opening is made through a dielectric layer overlying a substrate on a wafer. A copper layer is formed overlying the dielectric layer and completely filling the opening. The copper layer is polished back |
