| Patent Number |
Title Of Patent |
Date Issued |
| 7076634 |
Address translation manager and method for a logically partitioned computer system |
July 11, 2006 |
| An address translation manager creates a set of chained tables that may be allocated in non-contiguous physical memory, and that may be dynamically resized as needed. The chained tables comprise one or more tables that each correspond to a logical partition, with each table including a |
| 7028157 |
On-demand allocation of data structures to partitions |
April 11, 2006 |
| A method, apparatus, system, and signal-bearing medium that in an embodiment dynamically allocate and/or deallocate data structures on demand to respective partitions in a logically-partitioned electronic device. The data structures are associated with an adapter, and the partitions |
| 6934936 |
Apparatus and method for adaptive address-based historical utilization recording |
August 23, 2005 |
| An apparatus and method for recording segment execution times in a processing system are provided. The method includes the steps of recording a timestamp corresponding to the beginning of a segment to be executed, wherein the recording step is conducted through a firmware operation. The |
| 6665813 |
Method and apparatus for updateable flash memory design and recovery with minimal redundancy |
December 16, 2003 |
| A method and an apparatus is presented for updating flash memory that contains a write protected code, a first copy of rewritable recovery code, a second copy of rewritable recovery code, and a rewritable composite code. Each block of rewritable code contains a checksum code to detect if |
| 6233641 |
Apparatus and method of PCI routing in a bridge configuration |
May 15, 2001 |
| A primary PCI bus and multiple secondary PCI busses of a PCI expansion card interface, are interconnected by a routing circuit. The routing circuit functions as a switched bridge between the primary PCI bus and each of the secondary PCI busses, respectively, by associating each secondary |
| 6219761 |
Load/store assist engine |
April 17, 2001 |
| An input/output bus architecture that includes: an input/output bus; an input/output device connected to the input/output bus; a main processor, connected to the input/output bus, for executing a device driver corresponding to the input/output device, the device driver generating loa |
| 6085277 |
Interrupt and message batching apparatus and method |
July 4, 2000 |
| An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with |
| 6073253 |
Enhanced reset and built-in self-test mechanisms for single function and multifunction input/out |
June 6, 2000 |
| An apparatus, system and method permitting a variety of reset procedures and corresponding reset states. A device reset control register is provided for each I/O device adapter in single function or multifunction devices. The device reset control registers permit a greater degree of |
| 6023736 |
System for dynamically configuring I/O device adapters where a function configuration register c |
February 8, 2000 |
| An apparatus, system and method permitting dynamic configuration of I/O device adapters connected to a bus utilizes a function configuration register to store a READY/NOT READY status for each of the I/O device adapters. Upon the occurrence of a reset condition, dynamic configuration |
| 5983292 |
Message transport mechanisms and methods |
November 9, 1999 |
| An I/O system including a processor complex and system main memory connected to I/O adapters via I/O adapters and I/O bus. A message transport mechanism and method stores an upstream message queue and a downstream message queue in system main memory. Queue addresses are stored both i |
