| Patent Number |
Title Of Patent |
Date Issued |
| 7402194 |
Carbon nanotubes as low voltage field emission sources for particle precipitators |
July 22, 2008 |
| An air particle precipitator and a method of air filtration include a housing unit; a first conductor in the housing unit; a second conductor in the housing unit; and a carbon nanotube grown on the second conductor. Preferably, the first conductor is positioned opposite to the second |
| 7393779 |
Shrinking contact apertures through LPD oxide |
July 1, 2008 |
| Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical wa |
| 7387974 |
Methods for providing gate conductors on semiconductors and semiconductors formed thereby |
June 17, 2008 |
| A method of providing a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, binding a seed layer to the activated sites, and plating t |
| 7381655 |
Mandrel/trim alignment in SIT processing |
June 3, 2008 |
| Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern |
| 7381610 |
Semiconductor transistors with contact holes close to gates |
June 3, 2008 |
| A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically |
| 7378717 |
Semiconductor optical sensors |
May 27, 2008 |
| An optical sensor and method for forming the same. The optical sensor structure includes (a) a semiconductor substrate, (b) first, second, third, fourth, fifth, and sixth electrodes and (c) first, second, and third semiconducting regions. The first and fourth electrodes are at a firs |
| 7378678 |
Memory device and method of manufacturing the device by simultaneously conditioning transition m |
May 27, 2008 |
| Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially "U" shaped. The double memory cells comprise two essentially "U" shaped memory cells. Each memory cell comprises a memory element having a bi- |
| 7368712 |
Y-shaped carbon nanotubes as AFM probe for analyzing substrates with angled topography |
May 6, 2008 |
| A Y-shaped carbon nanotube atomic force microscope probe tip and methods comprise a shaft portion; a pair of angled arms extending from a same end of the shaft portion, wherein the shaft portion and the pair of angled arms comprise a chemically modified carbon nanotube, and wherein the |
| 7358140 |
Pattern density control using edge printing processes |
April 15, 2008 |
| A structure fabrication method. The method comprises providing a design structure that includes (i) a design substrate and (ii) M design normal regions on the design substrate, wherein M is a positive integer greater than 1. Next, N design sacrificial regions are added between two adjace |
| 7358120 |
Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM |
April 15, 2008 |
| A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper |
| 7352607 |
Non-volatile switching and memory devices using vertical nanotubes |
April 1, 2008 |
| Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Methods of sensing the state of the devices include measuring capacitance, and tunneling and field emis |
| 7352030 |
Semiconductor devices with buried isolation regions |
April 1, 2008 |
| Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing ad |
| 7351648 |
Methods for forming uniform lithographic features |
April 1, 2008 |
| Methods for fabricating a semiconductor device include forming a first layer on an underlying layer, forming a hardmask on the first layer, and patterning holes through the hardmask and first layer. An overhang is formed extending over sides of the holes. A conformal layer is deposited |
| 7348634 |
Shallow trench isolation formation |
March 25, 2008 |
| A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first |
| 7348610 |
Multiple layer and crystal plane orientation semiconductor substrate |
March 25, 2008 |
| A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor lay |
| 7345370 |
Wiring patterns formed by selective metal plating |
March 18, 2008 |
| Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are the |
| 7335930 |
Borderless contact structures |
February 26, 2008 |
| An SRAM cell. The SRAM cell including: a first gate segment common to a first PFET and a first NFET, a second gate segment common to a second PFET and a second NFET; a first silicide layer contacting a first end of the first gate segment and a drain of the second PFET; a second silicide |
| 7329613 |
Structure and method for forming semiconductor wiring levels using atomic layer deposition |
February 12, 2008 |
| A method for forming a conductive wire structure for a semiconductor device includes defining a mandrel on a substrate, forming a conductive wire material on the mandrel by atomic layer deposition, and forming a liner material around the conductive wire material by atomic layer depos |
| 7271079 |
Method of doping a gate electrode of a field effect transistor |
September 18, 2007 |
| A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of the substrate, a top |
| 7265013 |
Sidewall image transfer (SIT) technologies |
September 4, 2007 |
| A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer |
| 7256415 |
Memory device and method of manufacturing the device by simultaneously conditioning transition m |
August 14, 2007 |
| Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially "U" shaped. The double memory cells comprise two essentially "U" shaped memory cells. Each memory cell comprises a memory element having a bi- |
| 7256114 |
Process for oxide cap formation in semiconductor manufacturing |
August 14, 2007 |
| A process for forming a semiconductor device having an oxide beanie structure (an oxide cap overhanging an underlying portion of the device). An oxide layer is first provided covering that portion, with the layer having a top surface and a side surface. The top and side surfaces are |
| 7250347 |
Double-gate FETs (Field Effect Transistors) |
July 31, 2007 |
| A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping arou |
| 7233071 |
Low-k dielectric layer based upon carbon nanostructures |
June 19, 2007 |
| A low-k dielectric material for use in the manufacture of semiconductor devices, semiconductor structures using the low-k dielectric material, and methods of forming such dielectric materials and fabricating such structures. The low-k dielectric material comprises carbon nanostructur |
| 7233063 |
Borderless contact structures |
June 19, 2007 |
| A borderless contact structure and method of fabricating the structure, the method including: (a) providing a substrate; (b) forming a polysilicon line on the substrate, the polysilicon line having sidewalls; (c) forming an insulating sidewall layer on the sidewalls of the polysilico |
| 7230681 |
Method and apparatus for immersion lithography |
June 12, 2007 |
| An apparatus for holding a wafer and a method for immersion lithography. The apparatus, including a wafer chuck having a central circular vacuum platen, an outer region, and a circular groove centered on the vacuum platen, a top surface of the vacuum platen recessed below a top surface |
| 7229889 |
Methods for metal plating of gate conductors and semiconductors formed thereby |
June 12, 2007 |
| A method of metal plating a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, and binding a seed layer to the one or more of the act |
| 7227233 |
Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM |
June 5, 2007 |
| A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper |
| 7118997 |
Implantation of gate regions in semiconductor device fabrication |
October 10, 2006 |
| A method for implanting gate regions essentially without implanting regions of the semiconductor layer where source/drain regions will be later formed. The method includes the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, ( |
| 7087531 |
Shallow trench isolation formation |
August 8, 2006 |
| A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first |
| 7084060 |
Forming capping layer over metal wire structure using selective atomic layer deposition |
August 1, 2006 |
| Methods of forming a capping layer over a metal wire structure of a semiconductor device are disclosed. In one embodiment, the method includes providing a partially fabricated semiconductor device having exposed surfaces of the metal (e.g., copper) wire structure and a dielectric aro |
| 7074666 |
Borderless contact structures |
July 11, 2006 |
| A borderless contact structure and method of fabricating the structure, the method including: (a) providing a substrate; (b) forming a polysilicon line on the substrate, the polysilicon line having sidewalls; (c) forming an insulating sidewall layer on the sidewalls of the polysilico |
| 7071047 |
Method of forming buried isolation regions in semiconductor substrates and semiconductor devices |
July 4, 2006 |
| Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing ad |
| 7026259 |
Liquid-filled balloons for immersion lithography |
April 11, 2006 |
| A liquid-filled balloon may be positioned between a workpiece, such as a semiconductor structure covered with a photoresist, and a lithography light source. The balloon includes a thin membrane that exhibits good optical and physical properties. Liquid contained in the balloon also e |
| 6998204 |
Alternating phase mask built by additive film deposition |
February 14, 2006 |
| The invention provides a method of forming a phase shift mask and the resulting phase shift mask. The method forms a non-transparent film on a transparent substrate and patterns an etch stop layer on the non-transparent film. The invention patterns the non-transparent film using the |
| 6989323 |
Method for forming narrow gate structures on sidewalls of a lithographically defined sacrificial |
January 24, 2006 |
| A method for forming a gate structure for a semiconductor device includes defining a conductive sacrificial structure on a substrate, forming a reacted metal film on sidewalls of the conductive sacrificial structure, and removing unreacted portions of the conductive sacrificial structure |
| 6875685 |
Method of forming gas dielectric with support structure |
April 5, 2005 |
| A method for forming a gas dielectric with support structure on a semiconductor device structure provides low capacitance and adequate support for a conductor of the semiconductor device structure. A conductive structure, such as via or interconnect, is formed in a wing-layer dielect |
| 6531375 |
Method of forming a body contact using BOX modification |
March 11, 2003 |
| A novel method for forming substrate contact regions on a SOI substrate without requiring additional space, and in order to provide lower diffusion capacitance. The method utilizes known semiconductor processing techniques. This method for selectively modifying the BOX region of a SOI |
| 6503813 |
Method and structure for forming a trench in a semiconductor substrate |
January 7, 2003 |
| A method and structure for forming a trench in a semiconductor substrate that includes a semiconductor material such as silicon. The method and structure may be used to form a deep trench or a shallow trench, without having a pad oxide in contact with the semiconductor substrate. The met |
| 6498096 |
Borderless contact to diffusion with respect to gate conductor and methods for fabricating |
December 24, 2002 |
| A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following |
| 6294449 |
Self-aligned contact for closely spaced transistors |
September 25, 2001 |
| A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gat |
| 6215190 |
Borderless contact to diffusion with respect to gate conductor and methods for fabricating |
April 10, 2001 |
| A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following |
| 5605862 |
Process for making low-leakage contacts |
February 25, 1997 |
| A semiconductor device having low-leakage borderless contacts is formed by etching contact openings adjacent first and second electronic elements of opposite dopant type, conformally depositing a thin doped polysilicon layer, protecting the electronic element of similar dopant-type, remo |
| 5545581 |
Plug strap process utilizing selective nitride and oxide etches |
August 13, 1996 |
| The invention provides a method for electrically connecting a trench capacitor and a diffusion region, and also for electrically connecting a trench capacitor or a diffusion region with external circuitry in a semiconductor device. The method provides for formation of a strap or brid |
| 5173439 |
Forming wide dielectric-filled isolation trenches in semi-conductors |
December 22, 1992 |
| A method of forming a planarized dielectric filled wide shallow trench in a semi-conductor substrate is provided. A layer of etch stop such as Si.sub.3 N.sub.4 is deposited onto the semi-conductor substrate, and wide trenches are formed through the Si.sub.3 N.sub.4 into the substrate by |
| 4944682 |
Method of forming borderless contacts |
July 31, 1990 |
| A method of forming semi-conductor devices components wherein there are at least two exposed conducting regions having passivating material overlying said regions. The passivating material is subject to etching by a given etchant. At least one, but less than all of the regions are covere |
| 4799990 |
Method of self-aligning a trench isolation structure to an implanted well region |
January 24, 1989 |
| A method for self-aligning an isolation structure to a diffusion region. A first masking layer is formed on a semiconductor substrate, the first masking layer having at least one aperture sidewall which is substantially perpendicular to the semiconductor substrate. Dopant ions are implan |
| 4558508 |
Process of making dual well CMOS semiconductor structure with aligned field-dopings using single |
December 17, 1985 |
| A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographi |
| 4556585 |
Vertically isolated complementary transistors |
December 3, 1985 |
| A process for making complementary transistor devices in an epitaxial layer of a first conductivity type having a deep vertical isolation sidewall between the N and P channel transistors by providing a backfilled cavity in the epitaxial layer, the sidewalls of the cavity being coated wit |
| 4389257 |
Fabrication method for high conductivity, void-free polysilicon-silicide integrated circuit elec |
June 21, 1983 |
| A method of providing self-passivating interconnection electrodes for semiconductor devices which provides low resistivity composite polysiliconsilicide electrodes. In the method the formation of oxidation induced voids in polysilicon underlying the silicide is eliminated by depositi |
