| Patent Number |
Title Of Patent |
Date Issued |
| 7429494 |
Microelectronic imagers with optical devices having integral reference features and methods for |
September 30, 2008 |
| Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed herein. In one embodiment, the imager assembly can include a workpiece with a substrate having a front side, a back side, and |
| 7425499 |
Methods for forming interconnects in vias and microelectronic workpieces including such intercon |
September 16, 2008 |
| Methods for forming interconnects in blind vias or other types of holes, and microelectronic workpieces having such interconnects. The blind vias can be formed by first removing the bulk of the material from portions of the back side of the workpiece without thinning the entire workpiece |
| 7419841 |
Microelectronic imagers and methods of packaging microelectronic imagers |
September 2, 2008 |
| Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electricall |
| 7413979 |
Methods for forming vias in microelectronic devices, and methods for packaging microelectronic d |
August 19, 2008 |
| Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the |
| 7411304 |
Semiconductor interconnect having conductive spring contacts |
August 12, 2008 |
| An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conduc |
| 7410898 |
Methods of fabricating interconnects for semiconductor components |
August 12, 2008 |
| In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening a |
| 7409762 |
Method for fabricating an interconnect for semiconductor components |
August 12, 2008 |
| A method for fabricating an interconnect for testing a semiconductor component includes the steps of providing a substrate, and forming interconnect contacts on the substrate configured to electrically engage component contacts on the component. The interconnect contacts include flex |
| 7394267 |
Compliant contact pin assembly and card system |
July 1, 2008 |
| A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension |
| 7391117 |
Method for fabricating semiconductor components with conductive spring contacts |
June 24, 2008 |
| An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conduc |
| 7389581 |
Method of forming compliant contact structures |
June 24, 2008 |
| A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the substrate and at least |
| 7385412 |
Systems and methods for testing microfeature devices |
June 10, 2008 |
| Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual |
| 7378342 |
Methods for forming vias varying lateral dimensions |
May 27, 2008 |
| Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a second opening, and a third opening are formed in a substrate such that the first opening, the second opening, and the third openin |
| 7364985 |
Method for creating electrical pathways for semiconductor device structures using laser machinin |
April 29, 2008 |
| A method for creating electrical pathways for semiconductor device structures using laser machining processes is provided. The method of the present invention includes providing a semiconductor substrate and forming one or more depressions in the semiconductor substrate using laser m |
| 7363694 |
Method of testing using compliant contact structures, contactor cards and test system |
April 29, 2008 |
| A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the substrate and at least |
| 7358751 |
Contact pin assembly and contactor card |
April 15, 2008 |
| A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension |
| 7355267 |
Substrate, semiconductor die, multichip module, and system including a via structure comprising |
April 8, 2008 |
| A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hol |
| 7354863 |
Methods of selectively removing silicon |
April 8, 2008 |
| An etch solution that comprises tetramethylammonium hydroxide ("TMAH") and at least one organic solvent. The etch solution may be substantially free of water. The etch solution is formulated to selectively etch a silicon layer relative to other layers on an integrated circuit. The TMAH m |
| 7348671 |
Vias having varying diameters and fills for use with a semiconductor device and methods of formi |
March 25, 2008 |
| A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second openings through a semiconductor, wherein the first opening has a narrower width (smaller diameter) than the second opening. |
| 7332413 |
Semiconductor wafers including one or more reinforcement structures and methods of forming the s |
February 19, 2008 |
| Methods of forming semiconductor devices include thinning a region of a semiconductor wafer and forming at least one semiconductor die laterally within a thinned region of the wafer. One or more reinforcement structures may be defined on the wafer. Semiconductor wafers include one or |
| 7329943 |
Microelectronic devices and methods for forming interconnects in microelectronic devices |
February 12, 2008 |
| Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate |
| 7314821 |
Method for fabricating a semiconductor interconnect having conductive spring contacts |
January 1, 2008 |
| An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conduc |
| 7297563 |
Method of making contact pin card system |
November 20, 2007 |
| A compliant contact pin contactor card method for making is provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension |
| 7294897 |
Packaged microelectronic imagers and methods of packaging microelectronic imagers |
November 13, 2007 |
| Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrat |
| 7288954 |
Compliant contact pin test assembly and methods thereof |
October 30, 2007 |
| A compliant contact pin assembly and a contactor card and methods for testing therewith are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant cou |
| 7287326 |
Methods of forming a contact pin assembly |
October 30, 2007 |
| A compliant contact pin assembly method for making is provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within |
| 7282932 |
Compliant contact pin assembly, card system and methods thereof |
October 16, 2007 |
| A compliant contact pin assembly, a contactor card, a testing system and methods for making and testing are provided. A compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a |
| 7282784 |
Methods of manufacture of a via structure comprising a plurality of conductive elements and meth |
October 16, 2007 |
| A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hol |
| 7271482 |
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces f |
September 18, 2007 |
| Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having a plurality of microelectronic d |
| 7265330 |
Microelectronic imagers with optical devices and methods of manufacturing such microelectronic i |
September 4, 2007 |
| Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external |
| 7262134 |
Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
August 28, 2007 |
| Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a terminal and a diel |
| 7253397 |
Packaged microelectronic imagers and methods of packaging microelectronic imagers |
August 7, 2007 |
| Microelectronic imagers and methods of packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imager can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a plurality of terminals |
| 7244663 |
Wafer reinforcement structure and methods of fabrication |
July 17, 2007 |
| A method of fabricating a thinned, reinforced semiconductor wafer is disclosed. Particularly, a semiconductor wafer may be provided and a plurality of separate semiconductor dice may be formed upon a surface thereof. At least one region of the semiconductor wafer may be thinned and a |
| 7232754 |
Microelectronic devices and methods for forming interconnects in microelectronic devices |
June 19, 2007 |
| Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate |
| 7224051 |
Semiconductor component having plate and stacked dice |
May 29, 2007 |
| A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back sid |
| 7199439 |
Microelectronic imagers and methods of packaging microelectronic imagers |
April 3, 2007 |
| Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electricall |
| 7189954 |
Microelectronic imagers with optical devices and methods of manufacturing such microelectronic i |
March 13, 2007 |
| Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external |
| 7189642 |
Methods of fabricating interconnects including depositing a first material in the interconnect w |
March 13, 2007 |
| In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening a |
| 7169248 |
Methods for releasably attaching support members to microfeature workpieces and microfeature ass |
January 30, 2007 |
| Methods for releasably attaching support members to microfeature workpieces and microfeature assemblies formed using such methods. A method for processing a microfeature workpiece in accordance with one embodiment includes applying adhesive material to a non-active portion on a first |
| 7148715 |
Systems and methods for testing microelectronic imagers and microfeature devices |
December 12, 2006 |
| Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual |
| 7129567 |
Substrate, semiconductor die, multichip module, and system including a via structure comprising |
October 31, 2006 |
| Methods of forming at least one multiconductor via are disclosed. Specifically, a substrate may be provided and at least one through-hole may be formed therethrough. At least one seed layer may be formed, patterned, and a metal may be deposited thereon to form a plurality of conducti |
| 7109068 |
Through-substrate interconnect fabrication methods |
September 19, 2006 |
| A method for forming a conductive via or through-wafer interconnect (TWI) in a semiconductive substrate for use as a contact card, test connector, semiconductor package interposer, or die interconnect includes the acts of (a) forming an oxide or nitride layer on both sides of the substra |
| 7101792 |
Methods of plating via interconnects |
September 5, 2006 |
| Methods for filling high aspect ratio vias with conductive material. At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element forming a conductive structure of the semiconductor substr |
| 7091124 |
Methods for forming vias in microelectronic devices, and methods for packaging microelectronic d |
August 15, 2006 |
| Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the |
| 7078922 |
Semiconductor interconnect having semiconductor spring contacts |
July 18, 2006 |
| An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on the component. The interconnect contacts include flexible spring segments defined by grooves in the substrate |
| 7071098 |
Methods of fabricating interconnects for semiconductor components including a through hole entir |
July 4, 2006 |
| In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening a |
| 7064010 |
Methods of coating and singulating wafers |
June 20, 2006 |
| Separating and coating semiconductor dice at the wafer level to form individual chip-scale packages. In one embodiment, channels are formed in the active surface of a wafer to expose side surfaces of semiconductor dice. The surfaces of the channels are then etched to remove defects r |
| 7060526 |
Wafer level methods for fabricating multi-dice chip scale semiconductor components |
June 13, 2006 |
| A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back sid |
| 7053641 |
Interconnect having spring contacts |
May 30, 2006 |
| An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on the component. The interconnect contacts include flexible spring segments defined by grooves in the substrate |
| 7042080 |
Semiconductor interconnect having compliant conductive contacts |
May 9, 2006 |
| An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conduc |
| 7030632 |
Compliant contract structures, contactor cards and test system including same |
April 18, 2006 |
| A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the substrate and at least |
