| Patent Number |
Title Of Patent |
Date Issued |
| 7419859 |
Method of fabricating a semiconductor device having a single gate electrode corresponding to a p |
September 2, 2008 |
| Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods fo |
| 7361554 |
Multi-bit non-volatile memory device, method of operating the same, and method of manufacturing |
April 22, 2008 |
| Disclosed are a multi-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the multi-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of |
| 7352037 |
Semiconductor device and random access memory having single gate electrode corresponding to a pa |
April 1, 2008 |
| A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically conne |
| 7348535 |
Metal line structure of optical scanner and method of fabricating the same |
March 25, 2008 |
| A metal line structure of an optical scanner and a method of fabricating the same are provided. The metal line structure of the optical scanner includes: a glass substrate having a metal line region etched to a predetermined depth; a metal line formed in the metal line region; a diff |
| 7294855 |
Contact structure of semiconductor device, manufacturing method thereof, thin film transistor ar |
November 13, 2007 |
| Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portio |
| 7282759 |
Memory device having serially connected resistance nodes |
October 16, 2007 |
| A memory device may include a plurality of resistance nodes. The resistance nodes may be connected serially in a NAND or AND structure, by a plurality of metal plugs. The metal plugs may have a lower resistance. A control device corresponding to each resistance node may control the r |
| 7276765 |
Buried transistors for silicon on insulator technology |
October 2, 2007 |
| A buried transistor particularly suitable for SOI technology, where the transistor is fabricated within a trench in a substrate and the resulting transistor incorporates completely isolated active areas. The resulting substrate has a decreased topography and there is no need for polysili |
| 7274513 |
Off-axis projection optics and extreme ultraviolet lithography apparatus employing the same |
September 25, 2007 |
| Off-axis projection optics that includes first and second mirrors positioned off-axis and sharing a confocal point that are arranged to reduce linear astigmatism. If a distance between an object plane and the first mirror is l.sub.1, an incident angle of light coming from the object |
| 7256447 |
Multi-bit non-volatile memory device, method of operating the same, and method of manufacturing |
August 14, 2007 |
| Disclosed are a muli-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the muli-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of chann |
| 7247227 |
Buffer layer in flat panel display |
July 24, 2007 |
| In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fab |
| 7192873 |
Method of manufacturing nano scale semiconductor device using nano particles |
March 20, 2007 |
| Provided is a method of manufacturing a nano scale semiconductor device, such as a nano scale P-N junction device or a CMOS using nano particles without using a mask or a fine pattern. The method includes dispersing uniformly a plurality of nano particles on a semiconductor substrate, |
| 6900500 |
Buried transistors for silicon on insulator technology |
May 31, 2005 |
| A buried transistor particularly suitable for SOI technology, where the transistor is fabricated within a trench in a substrate and the resulting transistor incorporates completely isolated active areas. The resulting substrate has a decreased topography and there is no need for polysili |
| 6838835 |
Conductive spacer for field emission displays and method |
January 4, 2005 |
| Methods of operating field emission displays are disclosed. In one embodiment, a method for operating a field emission display includes applying a voltage to an extraction grid with respect to an emitter in proximity to the extraction grid to extract electrons from the emitter, regul |
| 6716081 |
Spacer fabrication for flat panel displays |
April 6, 2004 |
| A multi-layered structure, and method for producing same, which may include at least one glass layer anodically bonded to an intermediate layer. The intermediate layer may function as an anodic bonding layer, an etch stop layer, and/or a hard mask layer. A template may be formed of the |
| 6525462 |
Conductive spacer for field emission displays and method |
February 25, 2003 |
| A display includes a baseplate and an emitter formed on the baseplate. The display also includes a faceplate having a cathodoluminescent coating on a surface facing the baseplate and the emitter. A plurality of spacers separate the faceplate and the baseplate to prevent bowing of the |
| 6491561 |
Conductive spacer for field emission displays and method |
December 10, 2002 |
| Methods of manufacturing faceplates for field emission displays are disclosed. In one embodiment, a method for manufacturing a faceplate includes forming a transparent conductive layer on a transparent viewing screen, forming an insulating layer on the transparent conductive layer, a |
| 6471879 |
Buffer layer in flat panel display |
October 29, 2002 |
| In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fab |
| 6413135 |
Spacer fabrication for flat panel displays |
July 2, 2002 |
| A multi-layered structure, and method for producing same, which may include at least one glass layer anodically bonded to an intermediate layer. The intermediate layer may function as a anodic bonding layer, an etch stop layer, and/or a hard mask layer. A template may be formed of the |
| 6322712 |
Buffer layer in flat panel display |
November 27, 2001 |
| In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fab |
| 5851918 |
Methods of fabricating liquid crystal display elements and interconnects therefor |
December 22, 1998 |
| Methods of fabricating a liquid crystal display element on a substrate includes forming a thin film transistor on the substrate, the thin film transistor including a gate electrode covered by a channel region and a gate pad conductively connected to the gate electrode. A pad electrode is |
| 5444026 |
Method for manufacturing semiconductor device by forming insulator-layer to suppress bubble form |
August 22, 1995 |
| The present invention forms a intermediate layer between a conductive layer and BPSG layer. In one embodiment, this intermediate layer is a buffer layer that absorbs excess P ions from the BPSG layer to suppress the formation of bubbles and thereby prevent short circuits that may be caus |
