| Patent Number |
Title Of Patent |
Date Issued |
| 7411240 |
Integrated circuits including spacers that extend beneath a conductive line |
August 12, 2008 |
| Integrated circuit devices are fabricated by fabricating a conductive line on an insulating layer on an integrated circuit substrate. The conductive line includes a bottom adjacent the insulating layer, a top remote from the insulating layer and first and second sidewalls therebetween. A |
| 7387931 |
Semiconductor memory device with vertical channel transistor and method of fabricating the same |
June 17, 2008 |
| In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one anoth |
| 7368352 |
Semiconductor devices having transistors with vertical channels and method of fabricating the sa |
May 6, 2008 |
| In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4F.sup.2. The semiconductor device comprises: a cell array region having a plurality of unit cells, each unit cell having a cell occupation area, repeatedly ali |
| 7348628 |
Vertical channel semiconductor devices and methods of manufacturing the same |
March 25, 2008 |
| Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the p |
| 7297998 |
Semiconductor devices having a buried and enlarged contact hole and methods of fabricating the s |
November 20, 2007 |
| According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit |
| 7074718 |
Method of fabricating a semiconductor device having a buried and enlarged contact hole |
July 11, 2006 |
| According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit |
| 6930341 |
Integrated circuits including insulating spacers that extend beneath a conductive line |
August 16, 2005 |
| Integrated circuit devices are fabricated by fabricating a conductive line on an insulating layer on an integrated circuit substrate. The conductive line includes a bottom adjacent the insulating layer, a top remote from the insulating layer and first and second sidewalls therebetween. A |
