| Patent Number |
Title Of Patent |
Date Issued |
| D505856 |
Electrical outlet cover plate |
June 7, 2005 |
|
| 7368931 |
On-chip self test circuit and self test method for signal distortion |
May 6, 2008 |
| There is provided an on-chip test circuit that is capable of measuring validity of an output signal within a chip without any external measuring device. The on-chip self test circuit implemented on the same chip as a test semiconductor device includes: a test load block for receiving a |
| 7365564 |
Apparatus and method for controlling on die termination |
April 29, 2008 |
| An apparatus for controlling an on die termination (ODT) includes a counting unit for receiving an external clock signal and a delay locked loop (DLL) clock signal, and counting the toggle number of each of external clock signal and the DLL clock signal from a preset number; a compar |
| 7362158 |
Level shifter and a display device having the same |
April 22, 2008 |
| A level shifter and a display device having the same are provided. In a level shifter, a first transistor includes a gate electrode receiving a first driving voltage, and a source electrode receiving an input signal through an input terminal. A second transistor includes a drain electrod |
| 7342412 |
Device for controlling on die termination |
March 11, 2008 |
| An on die termination (ODT) control device includes a latency block for buffering an ODT control signal to output a latency control signal by selecting one of a plurality of intermediate control signals, which are generated by sequentially delaying the buffered ODT control signal in |
| 7323900 |
Semiconductor memory device for adjusting impedance of data output driver |
January 29, 2008 |
| A semiconductor memory device includes a reference signal generating unit for generating a reference signal; a comparing unit for comparing the reference signal with a test signal applied to a test pad to output an adjusted value after adjusting the adjusted value until the test signal |
| 7317328 |
Test device for on die termination |
January 8, 2008 |
| An on die termination (ODT) test device includes: a control unit for selectively activating a plurality of pull-up signals and a plurality of pull-down signals by performing a logic operation to an ODT control signal for controlling a resistor of a termination terminal, an off chip d |
| 7277331 |
Semiconductor memory device for adjusting impedance of data output driver |
October 2, 2007 |
| An apparatus for comparing inputted signals by removing an offset voltage during adjusting an output impedance of a semiconductor memory device, includes a voltage comparator for comparing a first input signal applied to its positive input node with a second input signal applied to its |
| 7199628 |
Power supply apparatus for delay locked loop and method thereof |
April 3, 2007 |
| A DLL voltage supply device for use in a semiconductor memory device includes: a bandgap voltage generating means for generating a bandgap voltage by using an external power supply voltage; a voltage level shifter for increasing a voltage level of the bandgap voltage in order to outp |
| 7198499 |
Low voltage electricity distribution circuit |
April 3, 2007 |
| The low voltage electricity distribution circuit of the present invention is an electrical outlet that includes a receptacle mounted to a recess including either a plurality of wires or a bus bar system. The receptacle has at least one continuously live power socket and at least one swit |
| 7176761 |
Apparatus and method for receiving inputted signal |
February 13, 2007 |
| An input signal receiver of a semiconductor device includes a gain control unit for outputting a gain control signal and a variable gain amplifier for amplifying external clock in response to the gain control signal, wherein the gain control signal determines a gain of the variable gain |
| 7109774 |
Delay locked loop (DLL) circuit and method for locking clock delay by using the same |
September 19, 2006 |
| A delay line unit of a delay locked loop (DLL) circuit, includes a first delay line having a plurality of first unit delays, each first unit delay having a first delay; a second delay line having a plurality of second unit delays, each second unit delay having a second delay; and a third |
| 6989700 |
Delay locked loop in semiconductor memory device and its clock locking method |
January 24, 2006 |
| A delay locked loop (DLL) for generating a delay locked clock signal, including: a comparator enable signal generator for generating a comparator enable signal in response to a reset signal and a plurality of clock divided signals; a semi locking detector for generating a semi lockin |
| 6987408 |
Digital delay locked loop and control method thereof |
January 17, 2006 |
| There is provided a digital delay locked loop (DLL) which is capable of minimizing a jitter by predicting and detecting a maximum jitter timing. The digital delay locked loop includes: a clock generator for generating a source clock and a reference clock; a delay line provided with a |
| 6903358 |
Paper thickness detecting device |
June 7, 2005 |
| Embodiments of the present invention relate to an apparatus (i.e. an automatic teller machine) comprising an optical sensor. The optical sensor is configured to detect thickness of paper. Advantages of some embodiments of the present invention are that by determining a thickness of paper |
| 6894539 |
Delay locked loop having phase comparator |
May 17, 2005 |
| A delay locked loop features a phase comparator. The phase comparator compares a phase of a reference clock signal obtained by dividing a buffered external clock signal with a phase of a feedback clock signal considering delay time of delay lines and inside circuits, and controls a s |
| 6876029 |
Integrated circuit capacitors having doped HSG electrodes |
April 5, 2005 |
| Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conducti |
| 6859404 |
Apparatus and method of compensating for phase delay in semiconductor device |
February 22, 2005 |
| An apparatus for minimizing a skew occurring due to a change of data pattern by previously recognizing data pattern before data is outputted from the semiconductor device. The apparatus of compensating for a phase delay in a semiconductor device having a delay locked loop (DLL) for g |
| 6822494 |
Register controlled delay locked loop |
November 23, 2004 |
| The present invention provides a register controlled delay locked loop (DLL) using an internal clock synchronized with an external clock as a delay monitoring clock source and a comparison standard clock source. The inventive register controlled DLL includes a first delay line; a second |
| 6624069 |
Methods of forming integrated circuit capacitors having doped HSG electrodes |
September 23, 2003 |
| Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conducti |
| 6370703 |
Odorless toilet |
April 16, 2002 |
| A toilet includes a fan configured to draw gases from the toilet bowl into the sewer line. The toilet also includes a tank assembly configured so that the tank contains a low water volume prior to the act of a user sitting on the toilet seat, and a high water volume when and after the |
| 6333227 |
Methods of forming hemispherical grain silicon electrodes by crystallizing the necks thereof |
December 25, 2001 |
| The crystallinity of non-monocrystalline silicon necks that connect monocrystalline silicon hemispherical grains to an underlying electrode on an integrated circuit substrate is increased. Preferably, the non-monocrystalline silicon necks are crystallized. By crystallizing the non-mo |
| 6218260 |
Methods of forming integrated circuit capacitors having improved electrode and dielectric layer |
April 17, 2001 |
| Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conducti |
| 5939131 |
Methods for forming capacitors including rapid thermal oxidation |
August 17, 1999 |
| A method for forming a microelectronic capacitor includes the steps of forming a first conductive layer on a substrate and forming an oxide reducing layer on the first conductive layer opposite the substrate wherein the oxide reducing layer reduces oxidation of the first conductive l |
| 5900163 |
Methods for performing plasma etching operations on microelectronic structures |
May 4, 1999 |
| A method for etching a layer of a microelectronic structure includes the steps of masking the layer to be etched so that predetermined portions of the layer are exposed, and providing an etching gas. An additional gas is also provided wherein the additional gas generates a compound havin |
| 5859760 |
Microelectronic capacitors having tantalum pentoxide dielectrics and oxygen barriers |
January 12, 1999 |
| A microelectronic capacitor is formed by nitrating the surface of a conducting electrode on a microelectronic substrate. The nitrated surface of the conductive electrode is then oxidized. The nitrating and oxidizing steps collectively form a film of silicon oxynitride on the conductive |
| 5763300 |
Method of fabricating microelectronic capacitors having tantalum pentoxide dielectrics and oxyge |
June 9, 1998 |
| A microelectronic capacitor is formed by nitrating the surface of a conducting electrode on a microelectronic substrate. The nitrated surface of the conductive electrode is then oxidized. The nitrating and oxidizing steps collectively form a film of silicon oxynitride on the conductive |
| 5721153 |
Method of making capacitor of highly integrated semiconductor device using multiple insulation l |
February 24, 1998 |
| A capacitor of a highly integrated semiconductor device and a manufacturing method thereof is provided. In the highly integrated semiconductor device, an HSG polysilicon layer pattern is formed having a multitude of hemispherical grains (HSG) on the top and side surfaces of the storage |
| 5324679 |
Method for manufacturing a semiconductor device having increased surface area conductive layer |
June 28, 1994 |
| A semiconductor device having a capacitor of large capacitance and the fabrication method thereof are disclosed. The semiconductor device comprises; a first electrode composed of a conductive structure whose entire surface, including sidewalls, are uneven and formed on the semiconduc |
| 4673477 |
Controlled vacuum arc material deposition, method and apparatus |
June 16, 1987 |
| A method and apparatus for vacuum arc deposition of material on a surface of an object uses a vacuum chamber accommodating the active surface of the cathode and an anode. A power supply connected to the anode and cathode establishes an electric arc. The track of the arc is controlled wit |
