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Jae-hak Kim Patents
Inventor:
Kim; Jae-hak
Address:
Seoul, KR
No. of patents:
17
Patents:




Patent Number Title Of Patent Date Issued
7323407 Method of fabricating dual damascene interconnections of microelectronic device using diffusion January 29, 2008
Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen
7307014 Method of forming a via contact structure using a dual damascene process December 11, 2007
A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling
7192864 Method of forming interconnection lines for semiconductor device March 20, 2007
The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is f
7183195 Method of fabricating dual damascene interconnections of microelectronic device using hybrid low February 27, 2007
A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical pro
7064059 Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer June 20, 2006
There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is f
7041592 Method for forming a metal interconnection layer of a semiconductor device using a modified dual May 9, 2006
A method for forming a metal interconnection layer of a semiconductor device comprises forming a film including a material selective to a medium used in an ashing process on an interlayer insulating film. The method comprises transforming the film during the ashing process to form an
7022600 Method of forming dual damascene interconnection using low-k dielectric material April 4, 2006
In order to avoid a faulty pattern resulting from a photoresist tail being formed due to a step difference of an upper hard mask layer when a dual hard mask layer is used, a planarization layer is formed following patterning of the upper hard mask layer. In this manner, a photoresist
6936533 Method of fabricating semiconductor devices having low dielectric interlayer insulation layer August 30, 2005
A method of fabricating a semiconductor device having a low dielectric constant is disclosed. According to the method, a silicon oxycarbide layer is formed, treated with plasma, and patterned. The silicon oxycarbide layer is formed by a coating method or a CVD method such as a PECVD
6861347 Method for forming metal wiring layer of semiconductor device March 1, 2005
A method for forming a metal wiring layer in a semiconductor device using a dual damascene process is provided. A stopper layer, an interlayer insulating layer, and a hard mask layer are sequentially formed on a semiconductor substrate having a conductive layer. A first photoresist p
6858727 Intermediate of carbapenem antibiotics and process for the preparation thereof February 22, 2005
There is disclosed an azetidinone compound of the formula (I): ##STR1##wherein R is hydrogen, or a hydroxy protecting group, R.sub.1 and R.sub.2 are each independently alkyl of 1-15 carbon atoms, benzyl or cyclized together with the carbon atom to which they are attached to form a 5 or
6855629 Method for forming a dual damascene wiring pattern in a semiconductor device February 15, 2005
In a method for forming a dual damascene wiring pattern, an etch stop film and an interlayer dielectric film comprising an SiOC:H group material are formed on a substrate having an electrical connection layer formed thereon. An anti-reflection layer is formed on the interlayer dielectric
6849536 Inter-metal dielectric patterns and method of forming the same February 1, 2005
Provided are an inter-metal dielectric pattern and a method of forming the same. The pattern includes a lower interconnection disposed on a semiconductor substrate, a lower dielectric layer having a via hole exposing the lower interconnection and covering the semiconductor substrate
6828229 Method of manufacturing interconnection line in semiconductor device December 7, 2004
A method of forming an interconnection line in a semiconductor device is provided. A first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching
6815331 Method for forming metal wiring layer of semiconductor device November 9, 2004
Methods for forming a metal wiring layer in a semiconductor device using a dual damascene process. In one aspect, a method for forming metal wiring in a semiconductor device comprises: forming a stopper layer on a semiconductor substrate that has a conductive layer formed thereon; fo
6432843 Methods of manufacturing integrated circuit devices in which a spin on glass insulation layer is August 13, 2002
An integrated circuit device is manufactured by forming a pattern on a substrate. The pattern may include two or more mesa regions. The pattern and the substrate are coated with a spin on glass layer and then the spin on glass layer is dissolved so that the spin on glass layer is recesse
5869477 .beta.-methylcarbapenem derivatives, process for the preparation thereof and pharmaceutical comp February 9, 1999
A .beta.-methylcarbapenem compound of formula (I), a salt or an ester thereof, a process for the preparation thereof and a anti-bacterial composition containing same: ##STR1## wherein: R.sup.1 is a C.sub.1-6 alkyl, C.sub.2-6 alkenyl, cycloalkyl, aryl or heterocyclic aryl group.
5453793 Method for recording a series program in a video cassette recorder September 26, 1995
Recording of a weekly serial TV program which is broadcast at least two times or more a week at designated times in a video cassette recorder having a system controller, wherein the system controller is provided with a memory and a timer for expressing a current time, a current day of th


 
 
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