| Patent Number |
Title Of Patent |
Date Issued |
| 7033900 |
Protection of integrated circuit gates during metallization processes |
April 25, 2006 |
| In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup. The gate of the |
| 5132936 |
MOS memory circuit with fast access time |
July 21, 1992 |
| An improved MOS memory circuit using an MOS clamp circuit on the bitlines which turns on when the voltage on a bitline exceeds a predetermined voltage, thereby drawing current from the bitline to remove excess charge and return the bitline to the predetermined voltage. The clamp circuit |
| 4837746 |
Method and apparatus for resetting a video SRAM |
June 6, 1989 |
| A method and apparatus for resetting a SRAM in a single DRAM-SRAM transfer cycle in a graphics system is described comprising a SRAM address decoder, a DRAM data input buffer, a reset data register and data lines. In operation, reset data is transferred into the DRAM data input buffer. |
| 4829471 |
Data load sequencer for multiple data line serializer |
May 9, 1989 |
| A data load serializer for use in conjunction with a multi-stage, multiple parallel data channel serializer is described. Each data channel of the data serializer preferably includes a data sensing stage and a data latching stage. The serializer is preferably responsive to the provision |
| 4817054 |
High speed RAM based data serializers |
March 28, 1989 |
| Multiple bit parallel data serializers are described for accessing data serially through a port at high video data rates. The serializer preferably comprises a buffer array for storing data at a plurality of SRAM memory locations, sense amplifiers for sensing the stored data, an addr |
| 4731758 |
Dual array memory with inter-array bi-directional data transfer |
March 15, 1988 |
| A high access speed memory for the internal storage of data and the addressable input/output transfer of data thereto, the memory comprising means for the dynamic storage of data, means for the static storage of data, and means for transferring data between the dynamic storage means |
| 4700370 |
High speed, low power, multi-bit, single edge-triggered, wraparound, binary counter |
October 13, 1987 |
| A high speed, low power, multi-bit, single edge triggered, wraparound binary counter is provided which is resettable and loadable from a user-supplied address. The binary counter requires a relatively small amount of power due to the use of CMOS technology for construction of its cir |
| 4438346 |
Regulated substrate bias generator for random access memory |
March 20, 1984 |
| An improved substrate bias generator is disclosed for use in a capacitive charge storage integrated circuit memory device having an external voltage supply. The generator comprises means for generating first and second timing signals, charge pumping means disposed for pumping positive ch |
| 4421996 |
Sense amplification scheme for random access memory |
December 20, 1983 |
| In source-clocked type of cross-coupled latch sense amplifier of a dynamic random access memory device, there is provided a sense clock that employs multiple extended dummy memory cells to provide reference timing which tracks time constants of word line, cell transfer gate, cell capacit |
