| Patent Number |
Title Of Patent |
Date Issued |
| 6658536 |
Cache-coherency protocol with recently read state for extending cache horizontally |
December 2, 2003 |
| A method of extending a cache of a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. A value is loaded from system memory into one or |
| 6314495 |
Method and apparatus for executing multiply-initiated, multiply-sourced variable delay system bu |
November 6, 2001 |
| The present invention is a method and apparatus for preventing the occurrence of deadlocks from the execution of multiply-initiated multiply-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon c |
| 6286068 |
Queued arbitration mechanism for data processing system |
September 4, 2001 |
| A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the sys |
| 6226695 |
Information handling system including non-disruptive command and data movement between storage a |
May 1, 2001 |
| An information handling system which efficiently processes auxiliary functions such as graphics processing includes one or more processors, a high speed processor bus connecting the one or more processors, a memory controller for controlling memory and for controlling the auxiliary f |
| 6202131 |
Method and apparatus for executing variable delay system bus operations of differing type or cha |
March 13, 2001 |
| A method and apparatus for preventing the occurrence of deadlocks from the execution of variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept |
| 6178485 |
Method and apparatus for executing singly-initiated, singly-sourced variable delay system bus op |
January 23, 2001 |
| The present invention is a method and apparatus for preventing the occurrence of deadlocks from the execution of singly-initiated singly-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condi |
| 6061757 |
Handling interrupts by returning and requeuing currently executing interrupts for later resubmis |
May 9, 2000 |
| An information handling system includes one or more processing units, a data management unit, connected to the processor data bus, to a memory system, and to an I/O bus, an address management unit, connected to the processor address bus, to the memory system, and to an I/O bus. Data |
| 6052762 |
Method and apparatus for reducing system snoop latency |
April 18, 2000 |
| In multi-processor systems which have separated the system bus from the I/O bus, a Shadow Directory is introduced into the memory controller for reducing bottlenecks that occur from the processors snooping data cache in the I/O devices residing on the I/O bus. This Shadow Directory is |
| 6029217 |
Queued arbitration mechanism for data processing system |
February 22, 2000 |
| A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the sys |
| 5996049 |
Cache-coherency protocol with recently read state for data and instructions |
November 30, 1999 |
| A method of providing instructions and data values to a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. Each cache of the process |
| 5963974 |
Cache intervention from a cache line exclusively holding an unmodified value |
October 5, 1999 |
| A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a cache, the cache is marked as containing an exclusively held, unmodified copy of the value |
| 5954825 |
Method for isolating faults on a clocked synchronous bus |
September 21, 1999 |
| A shift register is used to latch the bus-driver-enable signal for each potential bus driver during each system clock cycle. The shift register clock will freeze upon receipt of a "check stop" signal. Once frozen, the shift register can be scanned for fault isolation analysis. |
| 5946709 |
Shared intervention protocol for SMP bus using caches, snooping, tags and prioritizing |
August 31, 1999 |
| A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a plurality of caches, one cache is identified as a specific cache which contains an unmodifi |
| 5943685 |
Method of shared intervention via a single data provider among shared caches for SMP bus |
August 24, 1999 |
| A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. A requesting processing unit issues a message to an interconnect of the computer system indicating that the requesting processing unit desires to read a value from |
| 5940864 |
Shared memory-access priorization method for multiprocessors using caches and snoop responses |
August 17, 1999 |
| A method of reducing memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. When a requesting processing unit issues a message indicating that it desires to read a value from an address of a memory device of the computer system, each ca |
| 5940856 |
Cache intervention from only one of many cache lines sharing an unmodified value |
August 17, 1999 |
| A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into at least two caches, the caches are marked as containing shared, unmodified copies of the val |
| 5898896 |
Method and apparatus for data ordering of I/O transfers in Bi-modal Endian PowerPC systems |
April 27, 1999 |
| To present a consistent image of storage facilities to components in Bi-modal Endian PowerPC system enviromnents, provision is made for transferring data between system components in the appropriate Endian format. Endian conversion function can be incorporated into the memory control |
| 5790892 |
Information handling system for modifying coherency response set to allow intervention of a read |
August 4, 1998 |
| An information handling system includes a number of processors, each connected to a processor bus, a memory controller connected to the processor bus which controls access to a system memory, a system controller, and one or more I/O controllers connected to the system bus where the s |
| 5784710 |
Process and apparatus for address extension |
July 21, 1998 |
| Circuitry within a system memory controller of a data processing system enables an M-bit processor to address a memory location that requires an N-bit address, wherein N is greater than M. Thus, a less than 48-bit processor will be able to access IPL code resident within a 48-bit memory |
| 5771247 |
Low latency error reporting for high performance bus |
June 23, 1998 |
| A system and method are provided that use a determination of bad data parity and the state of an error signal (Derr.sub.--) as a functional signal indicating a specific type of error in a particular system component. If the Derr.sub.-- signal is active, the parity error recognized b |
| 5765022 |
System for transferring data from a source device to a target device in which the address of dat |
June 9, 1998 |
| PowerPC external control instructions are utilized to pass a translated address to a transfer engine located in the system memory controller, together with previously transferred parameters into control registers within the memory controller. An accelerated data movement is accomplished |
| 5745698 |
System and method for communicating between devices |
April 28, 1998 |
| A method and system are provided for communicating between devices. A signal is output from a first device. In response to the signal, at least one action is initiated by a second device. An indication is output of whether the second device completed the action and of whether operation o |
| 5734900 |
Information handling system including efficient power on initialization |
March 31, 1998 |
| An information handling system includes one or more processing units, a data management unit, connected to the processor data bus, to a memory system, and to a I/O bus, an address management unit, connected to the processor address bus, to the memory system, to an I/O bus, and to a s |
| 5713029 |
Information handling system including doze mode control |
January 27, 1998 |
| An information handling system includes a system memory controller having a control register in which a bit is reserved for Doze mode control. The Doze control bit is set by system software whenever it places any processor into Doze mode. Until this bit is set, there is no wake up si |
| 5687329 |
Information handling system including a data bus management unit, an address management unit for |
November 11, 1997 |
| An information handling system includes one or more processing units, a data bus management unit, connected to the processor data bus, to a memory system, and to an I/O bus, an address management unit, connected to the processor address bus, to the memory system, to the I/O bus, and one |
| 5687327 |
System and method for allocating bus resources in a data processing system |
November 11, 1997 |
| An efficient multiprocessor address transfer mechanism is utilized within a data processing system including a plurality of bus devices. The present invention places control of the flow of address bus operations within the system controller rather than the bus devices, e.g., a master pro |
| 5673413 |
Method and apparatus for coherency reporting in a multiprocessing system |
September 30, 1997 |
| An information processing system includes a plurality of bus devices coupled to at least one storage device via a bus. A first device (the "requestor") on a bus issues a request to obtain data and coherency information and monitors for the coherency information during a designated co |
| 5671370 |
Alternating data valid control signals for high performance data transfer |
September 23, 1997 |
| A system and method which utilizes a unique bus protocol in conjunctions plural Dval.sub.-- control signals to minimize the dead time between blocks of data being transferred between components is a data processing system. The present invention introduces another latch-to-latch data val |
| 5659708 |
Cache coherency in a multiprocessing system |
August 19, 1997 |
| A multiprocessor system utilizing a plurality of bus devices coupled via a shared bus utilizes a specially coded signal to notify a bus device initiating a read or a read with intent to modify operation that the requested data, or cache line, is in a modified state within a cache of |
