| Patent Number |
Title Of Patent |
Date Issued |
| 7391070 |
Semiconductor structures and memory device constructions |
June 24, 2008 |
| The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extendin |
| 7370306 |
Method and apparatus for designing a pattern on a semiconductor surface |
May 6, 2008 |
| A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a surface of a semiconductor wafer. Identified problem structures or regions in a pattern of el |
| 7364997 |
Methods of forming integrated circuitry and methods of forming local interconnects |
April 29, 2008 |
| In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the etching, a circuit c |
| 7335964 |
Semiconductor structures |
February 26, 2008 |
| In one aspect, the invention encompasses a semiconductor processing method of forming a material over an uneven surface topology. A substrate having an uneven surface topology is provided. The uneven surface topology comprises a valley between a pair of outwardly projecting features. A |
| 7326606 |
Semiconductor processing methods |
February 5, 2008 |
| In one aspect, the invention provides a method of forming a contact opening to a conductive line. In one preferred implementation, a contact opening is formed to a conductive line which overlies a substrate isolation area with an etch which also outwardly exposes substrate active are |
| 7290242 |
Pattern generation on a semiconductor surface |
October 30, 2007 |
| A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a surface of a semiconductor wafer. A pattern on a reticle is first generated using a medium su |
| 7288817 |
Reverse metal process for creating a metal silicide transistor gate structure |
October 30, 2007 |
| The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate ox |
| 7282401 |
Method and apparatus for a self-aligned recessed access device (RAD) transistor gate |
October 16, 2007 |
| A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor |
| 7262503 |
Semiconductor constructions |
August 28, 2007 |
| The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conducti |
| 7262473 |
Metal to polysilicon contact in oxygen environment |
August 28, 2007 |
| A method for forming a contact capable of tolerating an O.sub.2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down the metal oxide front of the metal layer at the metal-polysilicon interface, the metal layer is surrounded by one or more oxy |
| 7235865 |
Methods for making nearly planar dielectric films in integrated circuits |
June 26, 2007 |
| In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers--the insulative layers |
| 7235480 |
Semiconductor processing methods of forming integrated circuitry and semiconductor processing me |
June 26, 2007 |
| Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material |
| 7196394 |
Method and apparatus for a deposited fill layer |
March 27, 2007 |
| A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Dev |
| 7125800 |
Methods for making nearly planar dielectric films in integrated circuits |
October 24, 2006 |
| In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers--the insulative layers |
| 7115512 |
Methods of forming semiconductor constructions |
October 3, 2006 |
| The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication |
| 7112542 |
Methods of forming materials between conductive electrical components, and insulating materials |
September 26, 2006 |
| Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within |
| 7098105 |
Methods for forming semiconductor structures |
August 29, 2006 |
| The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extendin |
| 7067880 |
Transistor gate structure |
June 27, 2006 |
| The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate ox |
| 7026717 |
Fill pattern generation for spin-on glass and related self-planarization deposition |
April 11, 2006 |
| A fill pattern for a semiconductor device. The device includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such that the top surfaces of |
| 6949430 |
Semiconductor processing methods |
September 27, 2005 |
| Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of |
| 6936899 |
Bit line contacts |
August 30, 2005 |
| Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically |
| 6934928 |
Method and apparatus for designing a pattern on a semiconductor surface |
August 23, 2005 |
| A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a surface of a semiconductor wafer. Identified problem structures or regions in a pattern of el |
| 6898779 |
Pattern generation on a semiconductor surface |
May 24, 2005 |
| A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a surface of a semiconductor wafer. A pattern on a reticle is first generated using a medium su |
| 6890858 |
Methods of forming materials over uneven surface topologies, and methods of forming insulative m |
May 10, 2005 |
| In one aspect, the invention encompasses a semiconductor processing method of forming a material over an uneven surface topology. A substrate having an uneven surface topology is provided. The uneven surface topology comprises a valley between a pair of outwardly projecting features. A |
| 6858526 |
Methods of forming materials between conductive electrical components, and insulating materials |
February 22, 2005 |
| The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conducti |
| 6844594 |
Minimally spaced gates and word lines |
January 18, 2005 |
| A method of forming minimally spaced word lines is described. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a tapered etch or spacers to achieve the desired width of the trench. A filler material fills th |
| 6838714 |
Low leakage diodes, including photodiodes |
January 4, 2005 |
| A photodiode for use in an imager having an improved charge leakage. The photodiode has a doped region that is spaced away from the field isolation to minimize charge leakage. A second embodiment of invention provides a second implant to improve charge leakage to the substrate. The photo |
| 6821855 |
Reverse metal process for creating a metal silicide transistor gate structure |
November 23, 2004 |
| The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate ox |
| 6821836 |
Disposable spacer |
November 23, 2004 |
| A disposable spacer for use in a semiconductor device fabrication process is formed of a germanium-silicon alloy. The germanium-silicon alloy may include a first portion (x) of germanium and a second portion (1-x) of silicon, wherein x is greater than about 0.2. |
| 6812160 |
Methods of forming materials between conductive electrical components, and insulating materials |
November 2, 2004 |
| Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. |
| 6812138 |
Fill pattern generation for spin-on glass and related self-planarization deposition |
November 2, 2004 |
| A method of fabricating a semiconductor device. The method produces a device that includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns su |
| 6809389 |
Fill pattern generation for spin-on glass and related self-planarization deposition |
October 26, 2004 |
| A reticle for manufacturing a semiconductor device. The reticle includes cutouts that permit material deposited through the reticle and onto a surface of a semiconductor device being manufactured to form the shape of the cutouts. Shapes defined in the cutouts and produced on the semi |
| 6806577 |
Fill pattern generation for spin-on glass and related self-planarization deposition |
October 19, 2004 |
| A fill pattern for a semiconductor device. The device includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such that the top surfaces of the |
| 6787465 |
Method of forming a metal to polysilicon contact in oxygen environment |
September 7, 2004 |
| A method for forming a contact capable of tolerating an O.sub.2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down the metal oxide front of the metal layer at the metal-polysilicon interface, the metal layer is surrounded by one or more oxy |
| 6777813 |
Fill pattern generation for spin-on-glass and related self-planarization deposition |
August 17, 2004 |
| A fill pattern for a semiconductor device such as a memory cell. The memory cell includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such |
| 6777297 |
Disposable spacer and method of forming and using same |
August 17, 2004 |
| A disposable spacer for use in a semiconductor device fabrication process is formed of a germanium-silicon alloy. The germanium-silicon alloy may include a first portion (x) of germanium and a second portion (1-x) of silicon, wherein x is greater than about 0.2. A method of forming the |
| 6753220 |
SEMICONDUCTOR PROCESSING METHODS OF FORMING DEVICES ON A SUBSTRATE, FORMING DEVICE ARRAYS ON A S |
June 22, 2004 |
| Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically |
| 6746917 |
Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line c |
June 8, 2004 |
| Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically |
| 6743644 |
Method of making a metallization line layout |
June 1, 2004 |
| The present invention relates to metallization line layouts that minimize focus offset sensitivity by a substantial elimination of thin isolated metallization line segments that are inadequately patterned during formation of a mask. The present invention also relates to a metallization |
| 6740583 |
Semiconductor processing methods of forming integrated circuitry and semiconductor processing me |
May 25, 2004 |
| Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of |
| 6677632 |
Method of forming a metal to polysilicon contact in oxygen environment |
January 13, 2004 |
| A method for forming a contact capable of tolerating an O.sub.2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down the metal oxide front of the metal layer at the metal-polysilicon interface, the metal layer is surrounded by one or more oxy |
| 6667531 |
Method and apparatus for a deposited fill layer |
December 23, 2003 |
| A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Dev |
| 6635917 |
Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line c |
October 21, 2003 |
| Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically |
| 6635558 |
Semiconductor processing methods of forming a contact opening to a conductive line and methods o |
October 21, 2003 |
| In one aspect, the invention provides a method of forming a contact opening to a conductive line. In one preferred implementation, a contact opening is formed to a conductive line which overlies a substrate isolation area with an etch which also outwardly exposes substrate active area to |
| 6630716 |
Disposable spacer |
October 7, 2003 |
| A disposable spacer for use in a semiconductor device fabrication process is formed of a germanium-silicon alloy. The germanium-silicon alloy may include a first portion (x) of germanium and a second portion (1-x) of silicon, wherein x is greater than about 0.2. |
| 6627933 |
Method of forming minimally spaced word lines |
September 30, 2003 |
| A method of forming minimally spaced word lines is disclosed. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a tapered etch or spacers to achieve the desired width of the trench. A filler material fills th |
| 6627549 |
Methods for making nearly planar dielectric films in integrated circuits |
September 30, 2003 |
| In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers--the insulative layers |
| 6620561 |
Method for designing photolithographic reticle layout, reticle, and photolithographic process |
September 16, 2003 |
| There are provided methods of creating a phase shift mask, comprising storing a file representing a binary mask layout as one or more cells, or as a hierarchy of a plurality of cells, at least some of which cells contain printable shapes; for each cell, determining if the cell contains |
| 6593203 |
Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line c |
July 15, 2003 |
| Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically |
| 6590250 |
DRAM capacitor array and integrated device array of substantially identically shaped devices |
July 8, 2003 |
| Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically |
