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Sang-Moo Jeong Patents
Inventor:
Jeong; Sang-Moo
Address:
Seoul, KR
No. of patents:
3
Patents:




Patent Number Title Of Patent Date Issued
7297998 Semiconductor devices having a buried and enlarged contact hole and methods of fabricating the s November 20, 2007
According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit
7074718 Method of fabricating a semiconductor device having a buried and enlarged contact hole July 11, 2006
According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit
6124184 Method for forming isolation region of semiconductor device September 26, 2000
A method for forming an isolation region of a semiconductor device includes the steps of forming first and second insulating layers on a substrate, removing the second insulating layer over an isolation region, forming an oxide layer by oxidizing the first insulating layer over the isola


 
 
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