| Patent Number |
Title Of Patent |
Date Issued |
| 7013443 |
Delay diagnosis method for semiconductor integrated circuit, computer program product for diagno |
March 14, 2006 |
| A delay diagnosis method is proposed that can avoid design steps from being retraced or repeated uselessly due to defective delay when we design a semiconductor integrated circuit including a plurality of blocks. This delay diagnosis method has the steps of inputting logic informatio |
| 6944840 |
Design method and system for achieving a minimum machine cycle for semiconductor integrated circ |
September 13, 2005 |
| Each flip-flop-to-flip-flop path delay and a target machine cycle obtained in the stages of physical design and packaging design are used as input, and with respect to a path in which the path delay is not less than the target machine cycle, a closed loop including the path is extracted, |
| 5544068 |
System and method for optimizing delays in semiconductor circuits |
August 6, 1996 |
| A control device and a storage device are provided. The storage device has a clock signal file for determining a delay reference value for a path, and a logic information file for holding description of elements in the path. The control device refers to the clock signal file and the logi |
| 5475611 |
Circuit structure, semiconductor integrated circuit and path routing method and apparatus theref |
December 12, 1995 |
| An interconnection path layout in a circuit structure having terminals arranged in rows, such as a semiconductor integrated circuit. Paths are first assigned to selected obstruction-free terminal pairs to be interconnected, and then bypasses are assigned to the remaining obstruction- |
| 5264390 |
Method of automatic wiring in a semiconductor device |
November 23, 1993 |
| A method of automatic wiring in a semiconductor integrated circuit device having four or more wiring layers, with the lowest layer being a terminal layer, is intended to overcome the prior art problem in which lower layers are mostly used for wiring and upper layers are not used efficien |
| 5231589 |
Input/output pin assignment method |
July 27, 1993 |
| For signal lines to be connected from an LSI device or a module including a plurality of LSI devices as a mounted part via input/output pins thereof to external devices, pin assignment positions are determined as follows. The signal lines are classified into groups depending on attribute |
| 5212107 |
Wiring method for semiconductor integrated circuits |
May 18, 1993 |
| A novel wiring method for multilayered semiconductor integrated circuits is disclosed. For example, a semiconductor integrated circuit of a 6-layered wiring structure can be formed with a first layer covered with gates, a second layer, a third layer, a fourth layer and a fifth layer maki |
| 4805113 |
Method of updating layout of circuit element |
February 14, 1989 |
| For the purpose of satisfying placement constraint prescribed by design rule data, a region to which a plurality of circuit elements appertain is displayed in such a way that this region is moved to such a position as to environ a part of the circuit elements and at the same time is supe |
