| Patent Number |
Title Of Patent |
Date Issued |
| 7417894 |
Single latch data circuit in a multiple level cell non-volatile memory device |
August 26, 2008 |
| A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a |
| 7408814 |
Method and apparatus for filtering output data |
August 5, 2008 |
| Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option. |
| 7394699 |
Sense amplifier for a non-volatile memory device |
July 1, 2008 |
| The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing transistor provides a |
| 7324383 |
Selective slow programming convergence in a flash memory device |
January 29, 2008 |
| A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify |
| 7227789 |
Method and apparatus for filtering output data |
June 5, 2007 |
| Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option. |
| 7173856 |
Sense amplifier for a non-volatile memory device |
February 6, 2007 |
| The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing transistor provides a |
