| Patent Number |
Title Of Patent |
Date Issued |
| 6809032 |
Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation usi |
October 26, 2004 |
| In another aspect of the present invention, a system for detecting an endpoint in a polishing process is provided. The system comprises a polishing tool, a controllable light source, a sensor, and a controller. The polishing tool is capable of polishing a surface of a semiconductor d |
| 6649533 |
Method and apparatus for forming an under bump metallurgy layer |
November 18, 2003 |
| A method and an apparatus for forming an under bump metallurgy layer over a contact pad area on an interconnect formed over a semiconductor substrate are provided which eliminate a pretreatment process for removing native oxide on the contact pad area prior to the deposition of the under |
| 6555479 |
Method for forming openings for conductive interconnects |
April 29, 2003 |
| A method for forming a conductive interconnect comprises forming a process layer over a structure layer and forming a mask over the process layer, the mask having an etch profile therein. An anisotropic etching process is performed to erode the mask and to form an etched region in the pr |
| 6555396 |
Method and apparatus for enhancing endpoint detection of a via etch |
April 29, 2003 |
| A method is provided to enhance endpoint detection during via etching in the processing of a semiconductor wafer. The method includes forming a first process layer and a second process layer above the first process layer. A first masking layer is formed above at least a portion of the |
| 6514858 |
Test structure for providing depth of polish feedback |
February 4, 2003 |
| A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of ope |
| 6489683 |
Variable grain size in conductors for semiconductor vias and trenches |
December 3, 2002 |
| A method is provided for forming conductive layers in semiconductor channels and vias by using ramped current densities for the electroplating process. The lower density currents are used initially to deposit a fine grain conductive layer in the vias and then higher densities are used to |
| 6489240 |
Method for forming copper interconnects |
December 3, 2002 |
| A method for forming a semiconductor having improved copper interconnects is provided. The method comprises forming a first dielectric layer above a first structure layer. Thereafter, a first opening is formed in the first dielectric layer, and a first copper layer is formed above the fi |
| 6468889 |
Backside contact for integrated circuit and method of forming same |
October 22, 2002 |
| A contact formed from the backside of an integrated circuit device includes a first conductive layer on a first surface of the integrated circuit device and a second conductive layer on a second surface of the device. The two conductive layers are coupled by way of an opening through the |
| 6448099 |
Method and apparatus for detecting voltage contrast in a semiconductor wafer |
September 10, 2002 |
| A method is used to test a semiconductor wafer for misaligned layers formed therein. The method comprises forming a plurality of electrically conductive connections on a surface of the semiconductor wafer. A portion of the electrically conductive connections are coupled to a voltage |
| 6413846 |
Contact each methodology and integration scheme |
July 2, 2002 |
| A method of forming conductive contacts or an integrated circuit device is disclosed herein. In one embodiment, the method comprises forming a transistor above a semiconducting substrate, and forming a first layer comprised of an orthosilicate glass material above the transistor and the |
| 6362526 |
Alloy barrier layers for semiconductors |
March 26, 2002 |
| A semiconductor barrier layer and manufacturing method therefor for copper interconnects which is a tantalum-titanium, tantalum-titanium nitride, tantalum-titanium sandwich. The tantalum in the tantalum-titanium alloy bonds strongly with the semiconductor dielectric, the tantalum-titaniu |
| 6346472 |
Manufacturing method for semiconductor metalization barrier |
February 12, 2002 |
| A semiconductor metalization barrier, and manufacturing method therefor, is provided which is deposited from an aqueous solution containing the Period 4 transition metals of chromium, nickel, and copper deposited on a palladium-activated copper bonding pad. |
| 6344691 |
Barrier materials for metal interconnect in a semiconductor device |
February 5, 2002 |
| A semiconductor device is provided with a tantalum layer to line the channels and vias of a semiconductor, a tungsten nitride layer at a low temperature on the tantalum layer, and a copper conductor layer on the tungsten nitride layer. The tungsten nitride acts as a highly efficient |
| 6340633 |
Method for ramped current density plating of semiconductor vias and trenches |
January 22, 2002 |
| A method is provided for forming conductive layers in semiconductor channels and vias by using ramped current densities for the electroplating process. The lower density currents are used initially to deposit a fine grain conductive layer in the vias and then higher densities are used to |
| 6320263 |
Semiconductor metalization barrier and manufacturing method therefor |
November 20, 2001 |
| A semiconductor metalization barrier, and manufacturing method therefor, is provided which is deposited from an aqueous solution containing the Period 4 transition metals of chromium, nickel, and copper deposited on a palladium-activated copper bonding pad. |
| 6261946 |
Method for forming semiconductor seed layers by high bias deposition |
July 17, 2001 |
| A method is provided for forming seed layers in a channel or via by applying a high bias to the material of the seed layer during deposition. This sputters off the seed layer overhang in order to reduce the electrical resistance of the seed layer, maintain its barrier effectiveness a |
| 6244210 |
Strength coil for ionized copper plasma deposition |
June 12, 2001 |
| A new type of plasma coil for use in ionized metal plasma deposition systems. This new coil provides significant added strength to prevent sagging or other mechanical deformation. The improved coil consists of a core of a high strength material such as Titanium, for example. The rigid |
| 6239021 |
Dual barrier and conductor deposition in a dual damascene process for semiconductors |
May 29, 2001 |
| An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, |
| 6232230 |
Semiconductor interconnect interface processing by high temperature deposition |
May 15, 2001 |
| A method is provided for forming adhesion/barrier/conductor layers on semiconductor wafers in vias by using a high temperature adhesion/barrier material deposition step. The adhesion/barrier material is deposited over a channel conductor in the semiconductor dielectric with the semicondu |
| 6228754 |
Method for forming semiconductor seed layers by inert gas sputter etching |
May 8, 2001 |
| A method is provided for forming seed layers in semiconductor device channels or vias by using an inert gas sputter etching technique. The technique etches back the seed layers which results in a reduction of seed layer overhang at the top of the channels or vias, thereby enhancing the |
| 6218078 |
Creation of an etch hardmask by spin-on technique |
April 17, 2001 |
| A system and method for etching structures in a layer of a semiconductor device are disclosed. The method and system include spinning-on a hardmask layer, patterning the hardmask layer, and etching the layer. The hardmask layer is disposed above the layer and has a high etch selectivity. |
| 6187670 |
Multi-stage method for forming optimized semiconductor seed layers |
February 13, 2001 |
| A method is provided for forming seed layers in semiconductor channel and via openings by using a two-stage approach after lining the channel and via openings with barrier material. First, a low temperature deposition of a seed layer is performed at below the 250.degree. C. at which cond |
| 6166427 |
Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application |
December 26, 2000 |
| A method for producing a dielectric layer in a semiconductor product includes two steps. The first step is forming a fluorinated layer (e.g. SiOF or fluorosilicate glass ("FSG")) which includes a material formed in part with fluorine. The second step is forming a fill layer (e.g. SiO |
| 6159851 |
Borderless vias with CVD barrier layer |
December 12, 2000 |
| Borderless vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an undercut, etched side surface of a lower metal feature. A metal, such as tungsten, is subsequently deposited to fill the borderless via. Embodiments inc |
| 6150268 |
Barrier materials for metal interconnect |
November 21, 2000 |
| A method is provided for manufacturing a semiconductor device by: depositing a tantalum layer to line the channels and vias of a semiconductor; depositing a tungsten nitride layer at a low temperature on the tantalum layer; and depositing a copper conductor layer on the tungsten nitr |
| 6147404 |
Dual barrier and conductor deposition in a dual damascene process for semiconductors |
November 14, 2000 |
| An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, |
| 6146993 |
Method for forming in-situ implanted semiconductor barrier layers |
November 14, 2000 |
| A method is provided for forming barrier layers in channel or via openings of semiconductors by using in-situ nitriding of barrier metals (Ta, Ti, or W) after they have been deposited in channel and via openings which will allow better control of the barrier metal/barrier material (Ta/Ta |
| 6117770 |
Method for implanting semiconductor conductive layers |
September 12, 2000 |
| A method for implanting copper conductive layers in channel or via openings with alloying elements, such as magnesium, boron, tin, and zirconium. The implantation is performed after conductive layer chemical-mechanical-polishing (CMP) using a surface barrier layer as an implant barri |
| 6103085 |
Electroplating uniformity by diffuser design |
August 15, 2000 |
| Workpieces, such as semiconductor wafers, are electroplated with improved thickness uniformity by providing a diffuser member intermediate the cathode and anode of a fountain-type electroplating apparatus. The diffuser or member has a pattern of openings specifically designed to prev |
| 6100181 |
Low dielectric constant coating of conductive material in a damascene process for semiconductors |
August 8, 2000 |
| A method for manufacturing an integrated circuit using damascene processes is provided in which planar surfaces subjected to chemical-mechanical polishing are protected by a protective low dielectric constant coating. The coatings are of organic silicon materials which are spun on and ba |
| 6080669 |
Semiconductor interconnect interface processing by high pressure deposition |
June 27, 2000 |
| A method is provided for forming metal layers in semiconductor channels or vias by using a very high pressure ionized metal deposition technique which results in improved sidewall step coverage with enhanced subsequent filling of the channel or vias by conductive materials. To obtain the |
| 6048790 |
Metalorganic decomposition deposition of thin conductive films on integrated circuits using redu |
April 11, 2000 |
| A method for depositing conductive material inside openings within an integrated circuit uses chemical solution deposition. The method includes applying the integrated circuit having the openings with a metalorganic decomposition precursor. The metalorganic decomposition precursor on the |
| 5969425 |
Borderless vias with CVD barrier layer |
October 19, 1999 |
| Borderless vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an undercut, etched side surface of a lower metal feature. A metal, such as tungsten, is subsequently deposited to fill the borderless via. Embodiments inc |
| 5918149 |
Deposition of a conductor in a via hole or trench |
June 29, 1999 |
| The present semiconductor device and method of fabrication thereof includes the provision of a trench or via hole in a dielectric, with a barrier layer thereon extending into the trench or via hole. A layer of titanium is provided over the barrier layer, also extending into the trench or |
| 5912508 |
Metal-semiconductor contact formed using nitrogen plasma |
June 15, 1999 |
| A low-resistance metal-semiconductor contact for use in integrated circuits includes a titanium silicide layer overlaying a semiconductor body. The top surface of the titanium silicide layer is a combination of silicides and titanium nitride formed by exposing the top surface to a nitrog |
| 5545592 |
Nitrogen treatment for metal-silicide contact |
August 13, 1996 |
| A low-resistance contact for use in integrated circuits is formed by creating a titanium silicide layer on a semiconductor body and treating the titanium silicide layer with active free nitrogen to form a surface comprised of titanium nitride. This titanium nitride surface is then ov |
