| Patent Number |
Title Of Patent |
Date Issued |
| 7183198 |
Method for forming a hardmask employing multiple independently formed layers of a capping materi |
February 27, 2007 |
| A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes th |
| 7169711 |
Method of using carbon spacers for critical dimension (CD) reduction |
January 30, 2007 |
| A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposi |
| 7141502 |
Slurry-less polishing for removal of excess interconnect material during fabrication of a silico |
November 28, 2006 |
| A method for Chemical-Mechanical Polishing utilizes a two step process. The first step utilizes a slurry with abrasive particles which become embedded into a conditioned polishing pad having small cavities in the surface. During the second step the slurry flow is discontinued and the |
| 7132306 |
Method of forming an interlevel dielectric layer employing dielectric etch-back process without |
November 7, 2006 |
| A method of forming an interlevel dielectric (ILD) layer forms a polymer sacrificial ILD on a substrate. After metallization structures are formed in the polymer sacrificial ILD layer, a low power etch back is performed on the sacrificial ILD layer. Dielectric material is non-conformally |
| 7084071 |
Use of multilayer amorphous carbon ARC stack to eliminate line warpage phenomenon |
August 1, 2006 |
| A method of producing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate and providing an amorphous carbon layer over the polysilicon material layer. The amorphous carbon layer comprises at least one undoped amorphous carbon layer and |
| 7015124 |
Use of amorphous carbon for gate patterning |
March 21, 2006 |
| A method of producing an integrated circuit includes providing a mask definition structure above a layer of conductive material and providing a mask above the layer of conductive material and in contact with at least a portion of the mask definition structure. The mask definition structu |
| 6927113 |
Semiconductor component and method of manufacture |
August 9, 2005 |
| A semiconductor component and a method for manufacturing the semiconductor component that mitigates electromigration and stress migration in a metallization system of the semiconductor component. A hardmask is formed over a dielectric layer and an opening is etched through the hardmask a |
| 6875664 |
Formation of amorphous carbon ARC stack having graded transition between amorphous carbon and AR |
April 5, 2005 |
| A method of forming an integrated circuit using an amorphous carbon hard mask involves providing an amorphous carbon material layer above a layer of conductive material and providing an anti-reflective coating (ARC) material layer above the amorphous carbon material. A transition region |
| 6869734 |
EUV reflective mask having a carbon film and a method of making such a mask |
March 22, 2005 |
| An exemplary embodiment relates to a mask for integrated circuit fabrication equipment. The mask includes a multilayer film and an amorphous carbon layer above the multilayer film. The multilayer film is at least partially relatively reflective to radiation having a wavelength of les |
| 6864556 |
CVD organic polymer film for advanced gate patterning |
March 8, 2005 |
| A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a patt |
| 6855627 |
Method of using amorphous carbon to prevent resist poisoning |
February 15, 2005 |
| An exemplary embodiment relates to a method of using an amorphous carbon layer to prevent photoresist poisoning. The method includes doping a first amorphous carbon layer located above a substrate, providing an oxide layer above the first amorphous carbon layer where the oxide layer has |
| 6831003 |
Continuous barrier for interconnect structure formed in porous dielectric material with minimize |
December 14, 2004 |
| For filling an interconnect opening within a porous dielectric material, a diffusion barrier material is deposited onto at least one sidewall of the interconnect opening. A thickness of the diffusion barrier material is equal to or greater than a radius of a pore opened at the sidewall t |
| 6803313 |
Method for forming a hardmask employing multiple independently formed layers of a pecvd material |
October 12, 2004 |
| A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that a |
| 6689684 |
Cu damascene interconnections using barrier/capping layer |
February 10, 2004 |
| Interconnects to an underlying Cu feature are formed with improved reliability by replacing a portion of the capping layer in the bottom of an opening in an overlying dielectric layer, e.g., an ILD, with a barrier material, such as Ta or TaN. During Ar sputter etching to round the ILD |
| 6673684 |
Use of diamond as a hard mask material |
January 6, 2004 |
| A method for producing an integrated circuit includes providing a diamond layer above a layer of conductive material. A cap layer is provided above the diamond layer and patterned to form a cap feature. The diamond layer is patterned according to the cap feature to form a mask, and at le |
| 6653202 |
Method of shallow trench isolation (STI) formation using amorphous carbon |
November 25, 2003 |
| An exemplary embodiment relates to a method of shallow trench isolation (STI) formation using amorphous carbon as a sacrificial polish stop layer. The method can include polishing a silicon dioxide layer located above a wafer, polishing portions of the silicon dioxide layer located in a |
| 6635943 |
Method and system for reducing charge gain and charge loss in interlayer dielectric formation |
October 21, 2003 |
| A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capable of gap filling while using on |
| 6596631 |
Method of forming copper interconnect capping layers with improved interface and adhesion |
July 22, 2003 |
| The integrity of the interface and adhesion between a barrier or capping layer and a Cu or Cu alloy interconnect member is significantly enhanced by delaying and/or slowly ramping up the introduction of silane to deposit a silicon nitride capping layer after treating the exposed planariz |
| 6559017 |
Method of using amorphous carbon as spacer material in a disposable spacer process |
May 6, 2003 |
| A method of using amorphous carbon as spacer material in a disposable spacer process can include forming amorphous carbon spacers at lateral side walls of a gate structure over a substrate, implanting dopants in the substrate to form source and drain regions, ashing away the amorphous |
| 6530340 |
Apparatus for manufacturing planar spin-on films |
March 11, 2003 |
| This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions c |
| 6518646 |
Semiconductor device with variable composition low-k inter-layer dielectric and method of making |
February 11, 2003 |
| Strong adhesion to doped low-k inter-layer dielectrics is provided by varying the composition of dopant near the surface layers of the inter-layer dielectric. The concentration of dopant is gradually increased from about zero atomic % at the interface between the inter-layer dielectr |
| 6495443 |
Method of re-working copper damascene wafers |
December 17, 2002 |
| A method of re-working a semiconductor device having a defective copper damascene interconnect structure, including the steps of obtaining a semiconductor wafer having at least one defect in a copper damascene interconnect structure; placing the wafer in an electrolyte in an electrol |
| 6492258 |
METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-.mu.M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOG |
December 10, 2002 |
| A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the |
| 6489230 |
Integration of low-k SiOF as inter-layer dielectric |
December 3, 2002 |
| A semiconductor device formed on a substrate includes at least one metal stack formed on the substrate. A fluorosilicate glass layer is formed on the at least one metal stack, where the fluorosilicate glass layer acts as an interlayer dielectric for the semiconductor device. The fluorosi |
| 6472336 |
Forming an encapsulating layer after deposition of a dielectric comprised of corrosive material |
October 29, 2002 |
| Insulating material is formed to surround interconnect structures of an integrated circuit. A first semiconductor wafer is placed in a reaction chamber for forming the insulating material surrounding the interconnect structures of the integrated circuit on the first semiconductor wafer. |
| 6444593 |
Surface treatment of low-K SiOF to prevent metal interaction |
September 3, 2002 |
| A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface |
| 6429121 |
Method of fabricating dual damascene with silicon carbide via mask/ARC |
August 6, 2002 |
| A silicon carbide via mask/ARC is formed in implementing trench first-via last dual damascene techniques with an attendant improvement in dimensional accuracy and increased efficiency. Embodiments include forming a silicon carbide mask having an extinction coefficient (k) of about -0.2 |
| 6429108 |
Non-volatile memory device with encapsulated tungsten gate and method of making same |
August 6, 2002 |
| A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell with silicon nitride capping and sidewall layers, thereby preventing deleter |
| 6420278 |
Method for improving the dielectric constant of silicon-based semiconductor materials |
July 16, 2002 |
| An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials in which the dielectric constant has been reduced by spinning on the dielectric to silicon wafers, eliminating soft bake steps, and heating the wafers to about 400.degree. |
| 6407009 |
Methods of manufacture of uniform spin-on films |
June 18, 2002 |
| This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions c |
| 6400030 |
Self-aligning vias for semiconductors |
June 4, 2002 |
| An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the firs |
| 6400023 |
Integration of low-k SiOF for damascene structure |
June 4, 2002 |
| An interlayer dielectric for a damascene structure includes a first etch stop layer formed on a substrate. A first interlayer dielectric layer containing fluorine is formed on the first etch stop layer by deposition. A second etch stop layer is formed on the first interlayer dielectric |
| 6388309 |
Apparatus and method for manufacturing semiconductors using low dielectric constant materials |
May 14, 2002 |
| An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun on, processed in chemical vap |
| 6387825 |
Solution flow-in for uniform deposition of spin-on films |
May 14, 2002 |
| This invention describes improved apparatus and methods for spin-on deposition of thin films applicable to the manufacture of semiconductor devices. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved m |
| 6361837 |
Method and system for modifying and densifying a porous film |
March 26, 2002 |
| The invention provides a system and a method for densifying a surface of a porous film. By reducing the porosity of a film, the method yields a densified film that is more impenetrable to subsequent liquid processes. The method comprises the steps of providing a film having an exposed |
| 6355546 |
Thermally grown protective oxide buffer layer for ARC removal |
March 12, 2002 |
| A thermally grown oxide buffer layer is formed on a silicon layer prior to depositing an ARC thereon, thereby preventing damage to the silicon layer during ARC removal. Embodiments include thermally growing a silicon oxide buffer layer on an amorphous or polycrystalline silicon layer by |
| 6346467 |
Method of making tungsten gate MOS transistor and memory cell by encapsulating |
February 12, 2002 |
| A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell by silicon nitride capping and sidewall layers. The inventive methodology ad |
| 6335273 |
Surface treatment of low-K SiOF to prevent metal interaction |
January 1, 2002 |
| A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the sur |
| 6329718 |
Method for reducing stress-induced voids for 0.25m.mu. and smaller semiconductor chip technology |
December 11, 2001 |
| A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the |
| 6317642 |
Apparatus and methods for uniform scan dispensing of spin-on materials |
November 13, 2001 |
| This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions c |
| 6291329 |
Protective oxide buffer layer for ARC removal |
September 18, 2001 |
| An oxide buffer layer is formed between an underlying silicon layer and overlying ARC to prevent damage to the silicon layer when removing the ARC. Embodiments include depositing a silicon oxide buffer layer on an amorphous or polycrystalline silicon layer by PCVD, LPCVD or high temp |
| 6281584 |
Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfac |
August 28, 2001 |
| A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface |
| 6271120 |
Method of enhanced silicide layer for advanced metal diffusion barrier layer application |
August 7, 2001 |
| A rapid thermal anneal (>600.degree. C.) in a nitrogen-containing atmosphere is used to form a barrier TiN layer at the bottom of contact openings. To form source and drain contacts, contact openings are etched in a dielectric down to a titanium silicide layer on top of doped regions |
| 6252303 |
Intergration of low-K SiOF as inter-layer dielectric |
June 26, 2001 |
| A semiconductor device formed on a substrate includes at least one metal stack formed on the substrate. A fluorosilicate glass layer is formed on the at least one metal stack, where the fluorosilicate glass layer acts as an interlayer dielectric for the semiconductor device. The fluorosi |
| 6235453 |
Low-k photoresist removal process |
May 22, 2001 |
| An integrated circuit and a method of removing photoresist is described. The process described uses a low oxygen gas or non-oxygen gas plasma that removes the photoresist and provides a protective surface layer over the low-k dielectric material. The low-k dielectric material is part of |
| 6225240 |
Rapid acceleration methods for global planarization of spin-on films |
May 1, 2001 |
| This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions c |
| 6211074 |
Methods and arrangements for reducing stress and preventing cracking in a silicide layer |
April 3, 2001 |
| Methods and arrangements that increase the process control during the fabrication of the control gate configuration in a non-volatile memory semiconductor device are provided. The methods and arrangements effectively prevent cracks from developing within a tungsten suicide layer that |
| 6200913 |
Cure process for manufacture of low dielectric constant interlevel dielectric layers |
March 13, 2001 |
| This invention comprises improvements in the ways in which spin-on dielectric layers are cured. A semiconductor wafer is coated with a precursor for a spin-on dielectric material, and after the solution is thinned and evened, the wafer is placed in a curing oven, optionally containin |
| 6197703 |
Apparatus and method for manufacturing semiconductors using low dielectric constant materials |
March 6, 2001 |
| An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun on, processed in chemical vap |
| 6177364 |
Integration of low-K SiOF for damascene structure |
January 23, 2001 |
| An interlayer dielectric for a damascene structure includes a first etch stop layer formed on a substrate. A first interlayer dielectric layer containing fluorine is formed on the first etch stop layer by deposition. A second etch stop layer is formed on the first interlayer dielectric |
