| Patent Number |
Title Of Patent |
Date Issued |
| 7412211 |
Method for implementing enhanced hand shake protocol in microelectronic communication systems |
August 12, 2008 |
| A method and apparatus are provided for implementing an enhanced hand shake protocol for microelectronic communication systems. A transmitter and a receiver is coupled together by a transmission link. The transmitter receives an idle input. The idle input is activated when the transm |
| 7408374 |
Systems and methods for controlling of electro-migration |
August 5, 2008 |
| Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing |
| 7399686 |
Method and apparatus for making coplanar dielectrically-isolated regions of different semiconduc |
July 15, 2008 |
| A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types, the semiconductor layers comprising first, |
| 7397261 |
Monitoring system for detecting and characterizing classes of leakage in CMOS devices |
July 8, 2008 |
| A universal leakage monitoring system (ULMS) to measure a plurality of leakage macros during the development of a manufacturing process or a normal operation period. The ULMS characterizes the leakage of both n-type and p-type CMOS devices on the gate dielectric leakage, the sub-thre |
| 7396762 |
Interconnect structures with linear repair layers and methods for forming such interconnection s |
July 8, 2008 |
| Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a conductive material, such |
| 7393730 |
Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of mak |
July 1, 2008 |
| In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second cr |
| 7384838 |
Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such s |
June 10, 2008 |
| Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate |
| 7358164 |
Crystal imprinting methods for fabricating substrates with thin active silicon layers |
April 15, 2008 |
| Methods of forming semiconductor structures characterized by a thin active silicon layer on an insulating substrate by a crystal imprinting or damascene approach. The methods include patterning an insulating layer to define a plurality of apertures, filling the apertures in the patterned |
| 7348280 |
Method for fabricating and BEOL interconnect structures with simultaneous formation of high-k an |
March 25, 2008 |
| A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second |
| 7339390 |
Systems and methods for controlling of electro-migration |
March 4, 2008 |
| Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing |
| 7335599 |
Method and apparatus for making coplanar isolated regions of different semiconductor materials o |
February 26, 2008 |
| A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, |
| 7305571 |
Power network reconfiguration using MEM switches |
December 4, 2007 |
| A structure and method for power distribution to a network for an integrated circuit chip complex are provided. The chip complex has at least two sectors, each having at least one power providing connection with at least one of said connections beings individually addressable by, and |
| 7268624 |
Differential amplifier offset voltage minimization independently from common mode voltage adjust |
September 11, 2007 |
| Offset voltages in differential amplifiers are minimized by controlling compensation currents through the load impedances of the amplifiers. The currents are varied while sensing the polarity of the offset voltage. When the polarity changes, the current values are latched to keep the |
| 7265696 |
Methods and apparatus for testing an integrated circuit |
September 4, 2007 |
| In a first aspect, a method of testing an analog circuit is provided. The method includes (1) providing the analog circuit with a screening circuit adapted to cause the analog circuit to function like a logic gate during a test; and (2) applying digital signals to the analog circuit to t |
| 7132821 |
Reference current generation system |
November 7, 2006 |
| Systems are provided for generating and distributing a plurality of reference currents on an integrated circuit. More particularly, an integrated circuit is provided which includes a reference current generating system. The reference current generating system includes a first referen |
| 7098070 |
Device and method for fabricating double-sided SOI wafer scale package with through via connecti |
August 29, 2006 |
| A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. A through buried oxide via connects the chip(s) t |
| 7086020 |
Circuits and methods for matching device characteristics for analog and mixed-signal designs |
August 1, 2006 |
| Circuit designs and methods are provided for matching device characteristics for, e.g., analog or mixed-signal semiconductor integrated circuit designs. In particular, circuit layout patterns and layout methods are provided which enable precise or proportional matching of circuit com |
| 7081842 |
Electronic component value trimming systems |
July 25, 2006 |
| Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a correspo |
| 6964892 |
N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same |
November 15, 2005 |
| An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration implantation, and an N-driver coupled to the boost gate stack. |
| 6891357 |
Reference current generation system and method |
May 10, 2005 |
| As disclosed herein, systems and methods are provided for generating and distributing a plurality of reference currents on an integrated circuit. In a particular embodiment, an integrated circuit is disclosed which includes a reference current generator adapted to generate a plurality of |
| 6831369 |
Semiconductor structure having in-situ formed unit resistors and method for fabrication |
December 14, 2004 |
| An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurali |
| 6828232 |
Semiconductor structure having in-situ formed unit resistors and method for fabrication |
December 7, 2004 |
| An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurali |
| 6823293 |
Hierarchical power supply noise monitoring device and system for very large scale integrated cir |
November 23, 2004 |
| A hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system includes a plurality of on-chip noise-monitoring devices distributed |
| 6794226 |
Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and meth |
September 21, 2004 |
| A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, |
| 6720602 |
Dynamic random access memory (DRAM) cell with folded bitline vertical transistor and method of p |
April 13, 2004 |
| A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating |
| 6700203 |
Semiconductor structure having in-situ formed unit resistors |
March 2, 2004 |
| An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurali |
| 6700161 |
Variable resistor structure and method for forming and programming a variable resistor for elect |
March 2, 2004 |
| A non-ablative structure and method for forming a variable resistor includes providing a programmable resistive element including two or more different conductive materials, and changing a resistance of the programmable resistive element to a finite value by heating the programmable |
| 6674676 |
Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture |
January 6, 2004 |
| A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechan |
| 6674673 |
Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture |
January 6, 2004 |
| A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechan |
| 6632741 |
Self-trimming method on looped patterns |
October 14, 2003 |
| A method of self-trimming pattern, includes forming a pattern containing a plurality of regular or irregular features within a first material deposited on a substrate, depositing a conformal layer of second material, and etching the second material to form spacers of the second material |
| 6603690 |
Low-power static column redundancy scheme for semiconductor memories |
August 5, 2003 |
| A static column redundancy scheme for a semiconductor memory such as an eDRAM. By utilizing the existing scan registers for SRAM array testing, the column redundancy information of each bank or each microcell of the memory chip can be scanned, stored and programmed during the power-on |
| 6552378 |
Ultra compact DRAM cell and method of making |
April 22, 2003 |
| A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transfer device formed in a substan |
| 6545339 |
Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and meth |
April 8, 2003 |
| A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, |
| 6529402 |
Low power static memory |
March 4, 2003 |
| A stacked block array architecture.for a SRAM memory for low power applications. The architecture turns on only the required data cells and sensing circuitry to access a particular set of data cells of interest. The wordline delay is reduced by using a shorter and wider wordline wire |
| 6512275 |
Semiconductor integrated circuits |
January 28, 2003 |
| A semiconductor apparatus and method for making the same is disclosed herein in which the semiconductor apparatus includes a first active device formed in a mesa region of semiconductor material formed on one or more sidewalls of an isolation region, and a conductive path which extends f |
| 6504777 |
Enhanced bitline equalization for hierarchical bitline architecture |
January 7, 2003 |
| In a high density dynamic memory circuit, the sense amplifiers are shared by several bitlines in order to maintain a high density and low power design. However, the bitline equalization level drifts after several cycles of operation, caused by an unbalanced capacitance resulting from a |
| 6504173 |
Dual gate FET and process |
January 7, 2003 |
| The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose o |
| 6495445 |
Semi-sacrificial diamond for air dielectric formation |
December 17, 2002 |
| Disclosed is a structure and process for incorporating air or other gas as a permanent dielectric medium in a multilevel chip by providing CVD diamond as a semi-sacrificial interlevel and intralevel dielectric material. The semi-sacrificial dielectric is subsequently at least partial |
| 6433397 |
N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same |
August 13, 2002 |
| An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration N-type implantation, and an N-driver coupled to the boost gate stack. |
| 6426903 |
Redundancy arrangement using a focused ion beam |
July 30, 2002 |
| A static redundancy arrangement for a circuit using a focused ion beam anti-fuse methodology which reduces the circuit layout area and the switching activity compared to a prior art dynamic redundancy scheme, resulting in less power, a simpler design and higher speed. Focused ion bea |
| 6424011 |
Mixed memory integration with NVRAM, dram and sram cell structures on same substrate |
July 23, 2002 |
| A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same semiconductor on insulator substrate. An NVRAM cell structure. Processes f |
| 6399447 |
Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transi |
June 4, 2002 |
| A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating |
| 6352882 |
Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipat |
March 5, 2002 |
| Doped polysilicon plugs are formed in contact with MOSFET device regions and passing through the buried oxide region into the opposite type silicon substrate of an SOI structure. The polysilicon plugs are in contact with the sources and drains of the MOSFET devices to provide paths for |
| 6343044 |
Super low-power generator system for embedded applications |
January 29, 2002 |
| A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consum |
| 6259126 |
Low cost mixed memory integration with FERAM |
July 10, 2001 |
| A semiconductor memory device including at least three different types of memory cell structures. The types include an NVRAM cell structure, an FERAM cell structure, a DRAM cell structure, and an SRAM cell structure. The cell structures are disposed on the same substrate. |
| 6232173 |
Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures |
May 15, 2001 |
| A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure, and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same substrate. An NVRAM cell structure. Processes for forming a memory struct |
| 6207530 |
Dual gate FET and process |
March 27, 2001 |
| The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose o |
| 6177299 |
Transistor having substantially isolated body and method of making the same |
January 23, 2001 |
| A method for forming a field effect transistor (FET) is disclosed which includes forming an isolation region in a substrate of semiconductor material, anisotropically etching the substrate such that a sidewall spacer region of semiconductor material remains on a sidewall of the isola |
| 6144081 |
Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structur |
November 7, 2000 |
| A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across |
| 6141267 |
Defect management engine for semiconductor memories and memory systems |
October 31, 2000 |
| A defect management engine (DME) for memories integrates a plurality of redundancy data cells and a plurality of redundancy address cells in the same array. The redundancy data cells are used for replacing defective cells in the memories. The redundancy address cells store the addresses |
