| Patent Number |
Title Of Patent |
Date Issued |
| 7447082 |
Method for operating single-poly non-volatile memory device |
November 4, 2008 |
| A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a |
| 7433243 |
Operation method of non-volatile memory |
October 7, 2008 |
| A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive t |
| 6920067 |
Integrated circuit embedded with single-poly non-volatile memory |
July 19, 2005 |
| A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS |
| 6914825 |
Semiconductor memory device having improved data retention |
July 5, 2005 |
| A NVM device encompasses a MOS select transistor including a select gate electrically connected to a word line, a first source doping region electrically connected to a source line, and a first drain doping region. A MOS floating gate transistor is serially electrically connected to the |
| 6842374 |
Method for operating N-channel electrically erasable programmable logic device |
January 11, 2005 |
| An electrically erasable programmable logic device (EEPLD) contains a P-type substrate. A first N-type doped region is disposed in the P-type substrate. A first gate, which is used to store data, overlies the P-type substrate and is adjacent to the first N-type doped region. A second |
| 6822286 |
Cmos-compatible read only memory and method for fabricating the same |
November 23, 2004 |
| A CMOS-compatible read only memory (ROM) includes a first single-poly PMOS transistor that is serially electrically connected to a second single-poly PMOS transistor for recording digital data "1" or digital data "0". The first and second single-poly PMOS transistors are both formed on a |
| 6812083 |
Fabrication method for non-volatile memory |
November 2, 2004 |
| A fabrication method for a non-volatile memory includes providing a first metal oxide semiconductor (MOS) transistor having a control gate and a second MOS transistor having a source, a drain, and a floating gate. The first MOS transistor and the second MOS transistor are formed on a wel |
| 6740556 |
Method for forming EPROM with low leakage |
May 25, 2004 |
| A method for forming an electrically programmable read-only memory(EPROM) includes forming a first p.sup.+ doped region, a second p.sup.+ doped region, and a third p.sup.+ doped region on an N-well, forming a control gate between the first p.sup.+ doped region and the second p.sup.+ dope |
| 6617637 |
Electrically erasable programmable logic device |
September 9, 2003 |
| An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P.sup.+ dope |
| 6417046 |
Modified nitride spacer for solving charge retention issue in floating gate memory cell |
July 9, 2002 |
| A modified nitride spacer and making of the same are disclosed. The modified nitride spacer is formed adjacent a high-temperature oxide (HTO) layer which in turn is formed adjacent the sidewalls of a gate electrode. It is shown that the placement of an intervening oxide layer between the |
| 6303454 |
Process for a snap-back flash EEPROM cell |
October 16, 2001 |
| The present invention provides method to fabricate a snap-back flash EEPROMS device. The method begins by forming a gate structure 22 24 28 26 on a substrate. The gate structure comprises: a tunnel oxide layer 22, a floating gate 24, integrate dielectric layer 28, and a control gate 26. |
| 6117732 |
Use of a metal contact structure to increase control gate coupling capacitance for a single poly |
September 12, 2000 |
| A method for fabricating a single polysilicon, non-volatile memory device, has been developed. The method features the use of a metal structure, comprised to contact an underlying control gate region, located in the semiconductor structure, in addition to providing the upper electrode, f |
| 6055183 |
Erase method of flash EEPROM by using snapback characteristic |
April 25, 2000 |
| A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles, while prev |
| 6049484 |
Erase method to improve flash EEPROM endurance by combining high voltage source erase and negati |
April 11, 2000 |
| A method to erase data from a flash EEPROM is disclosed. Electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. |
| 5949717 |
Method to improve flash EEPROM cell write/erase threshold voltage closure |
September 7, 1999 |
| A method to erase data from a flash EEPROM cell while electrical charges trapped in the tunnel oxide of a flash EEPROM cell are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. |
| 5903499 |
Method to erase a flash EEPROM using negative gate source erase followed by a high negative gate |
May 11, 1999 |
| A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method |
| 5862078 |
Mixed mode erase method to improve flash eeprom write/erase threshold closure |
January 19, 1999 |
| A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method |
| 5838618 |
Bi-modal erase method for eliminating cycling-induced flash EEPROM cell write/erase threshold cl |
November 17, 1998 |
| A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method |
| 5726933 |
Clipped sine shaped waveform to reduce the cycling-induced electron trapping in the tunneling ox |
March 10, 1998 |
| The present invention provides method to erase and program flash EEPROMS devices using a clipped sine waveform (Vg). The clipped sine waveform reduces the tunneling oxide electric field between the floating gate and the source or drain region thereby reducing electron trapping. The metho |
