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Noritoshi Hirano Patents
Inventor:
Hirano; Noritoshi
Address:
Fukuoka, JP
No. of patents:
7
Patents:




Patent Number Title Of Patent Date Issued
6614087 Semiconductor device September 2, 2003
An object is to provide a semiconductor device which is free from such voltage oscillation as may cause malfunction of peripheral equipment. In a semiconductor device having a pin structure, the impurity concentration gradient in an n.sup.+ layer (103) serving as a buffer layer is set eq
6552413 Diode April 22, 2003
Implemented is a diode which controls an energy loss produced during a reverse recovery operation and generates an oscillation of an applied voltage with difficulty even if a reverse bias voltage has a great value. An N layer 101 and a P layer 102 are formed in a semiconductor substrate
6521919 Semiconductor device of reduced thermal resistance and increased operating area February 18, 2003
A semiconductor device is composed a semiconductor substrate having a first conducting-type first semiconductor layer, a second conducting-type second semiconductor layer, a first conducting-type third semiconductor layer, a second conducting-type fourth semiconductor layer and a first
6489666 Semiconductor device with improved heat suppression in peripheral regions December 3, 2002
A semiconductor device (102) comprises an N type semiconductor substrate (1). A P layer (22) is formed in a first surface (S1) of the semiconductor substrate (1), and a P layer (23) is formed in the semiconductor substrate (1) and in contact with the first surface (S1) and a second surfa
6479882 Current-limiting device November 12, 2002
The current-limiting device 1 includes a silicon substrate 2 having surfaces opposite to each other, and two electrodes 3 deposited respectively on the opposite surfaces of the silicon substrate. The silicon substrate 2 is of a three-layered structure including an N- layer 4 of a low
6388306 Semiconductor device with rapid reverse recovery characteristic May 14, 2002
An object is to obtain a semiconductor device having a PN junction which can suppress voltage oscillation without exerting any adverse effects. The film thickness of the N.sup.- layer (101) is set to satisfy both of a first condition that the depletion layer extending in the N.sup.- laye
6388276 Reverse conducting thyristor May 14, 2002
Providing a reverse conducting thyristor, wherein a diode and a GTO thyristor are reverse parallel-connected, with which it is possible to reduce a surface area size of a separation portion and avoid variations in insulation characteristics.A separation portion between a diode and a GTO


 
 
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