| Patent Number |
Title Of Patent |
Date Issued |
| 7376816 |
Method and systems for executing load instructions that achieve sequential load consistency |
May 20, 2008 |
| A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal |
| 7302527 |
Systems and methods for executing load instructions that avoid order violations |
November 27, 2007 |
| Methods for executing load instructions are disclosed. In one method, a load instruction and corresponding thread information are received. Address information of the load instruction is used to generate an address of the needed data, and the address is used to search a cache memory |
| 6604173 |
System for controlling access to external cache memories of differing size |
August 5, 2003 |
| A method for controlling access to at least one external cache memory in a processing system, the at least one external cache memory having a number of lines of data and a number of bytes per line of data, the method includes determining a smallest cache memory size for use in the at lea |
| 5694573 |
Shared L2 support for inclusion property in split L1 data and instruction caches |
December 2, 1997 |
| A multi-processor data processing system has a multi-level cache wherein each processor has a split high level (e.g., level one or L1) cache composed of a data cache (DCache) and an instruction cache (ICache). A shared lower level (e.g., level two or L2) cache includes a cache array |
| 5692151 |
High performance/low cost access hazard detection in pipelined cache controller using comparator |
November 25, 1997 |
| An access hazard detection technique in a pipelined cache controller sustains high throughput in a frequently accessed cache but without the cost normally associated with such access hazard detection. If a previous request (request in the pipeline stages other than the first stage) has |
| 5584013 |
Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache i |
December 10, 1996 |
| The present invention provides balanced cache performance in a data processing system. The data processing system includes a first processor, a second processor, a first cache memory, a second memory and a control circuit. The first processor is connected to the first cache memory, which |
| 5581734 |
Multiprocessor system with shared cache and data input/output circuitry for transferring data am |
December 3, 1996 |
| A high performance shared cache is provided to support multiprocessor systems and allow maximum parallelism in accessing the cache by the processors, servicing one processor request in each machine cycle, reducing system response time and increasing system throughput. The shared cach |
