| Patent Number |
Title Of Patent |
Date Issued |
| 7445976 |
Method of forming a semiconductor device having an interlayer and structure therefor |
November 4, 2008 |
| A stack located over a substrate. The stack includes a layer between a dielectric layer and a metal layer. The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example the |
| 7439105 |
Metal gate with zirconium |
October 21, 2008 |
| A gate electrode (202) for a transistor including a metal gate structure (207) containing zirconium and a polycrystalline silicon cap (209) located there over. The metal gate structure (207) is located over a gate dielectric (205). The zirconium inhibits diffusion of silicon from the |
| 7091568 |
Electronic device including dielectric layer, and a process for forming the electronic device |
August 15, 2006 |
| A mixture of materials can be used within a layer of an electronic device to improve electrical and physical properties of the layer. In one set of embodiments, the layer can be a dielectric layer, such as a gate dielectric layer or a capacitor dielectric layer. The dielectric layer |
| 6717226 |
Transistor with layered high-K gate dielectric and method therefor |
April 6, 2004 |
| A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the |
| 6432779 |
Selective removal of a metal oxide dielectric |
August 13, 2002 |
| A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed portion of the metal oxide gate |
| 6383873 |
Process for forming a structure |
May 7, 2002 |
| A finished structure (100) includes a semiconductive region (102), a first oxide layer (106), a second oxide layer (108), and a conductive layer (110). The first oxide layer (106) lies between the semiconductive region (102) and the second oxide layer (108); and the second oxide layer (1 |
| 6300202 |
Selective removal of a metal oxide dielectric |
October 9, 2001 |
| A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed portion of the metal oxide gate |
| 6297173 |
Process for forming a semiconductor device |
October 2, 2001 |
| A method for forming an oxynitride gate dielectric layer (202, 204) begins by providing a semiconductor substrate (200). This semiconductor substrate is cleaned via process steps (10-28). Optional nitridation and oxidation are performed via steps (50 and 60) to form a thin interface laye |
| 6255204 |
Method for forming a semiconductor device |
July 3, 2001 |
| A first metal-containing material (22) is formed over a semiconductor device substrate (10). A second metal-containing material (32) is formed over the first metal containing material (22). The combination of the second metal-containing material (32) formed over the first metal-conta |
| 6187682 |
Inert plasma gas surface cleaning process performed insitu with physical vapor deposition (PVD) |
February 13, 2001 |
| A method for insitu performing a cleaning operation along with a physical sputtering operation begins by placing a wafer (26) into a chamber (12). A plasma (30) is generated within the chamber (12) using an inert, noble, or reducing gas. The gas is ionized to form ions (32) within the pl |
| 6136682 |
Method for forming a conductive structure having a composite or amorphous barrier layer |
October 24, 2000 |
| A method for forming an improved copper barrier layer begins by providing a silicon-containing layer (10). A physical vapor deposition process is then used to form a thin tantalum nitride amorphous layer (12). A thin amorphous titanium nitride layer (14) is then deposited over the amorph |
| 6020024 |
Method for forming high dielectric constant metal oxides |
February 1, 2000 |
| A method for forming a metal gate (20) structure begins by providing a semiconductor substrate (12). The semiconductor substrate (12) is cleaned to reduce trap sites. A nitrided layer (14) having a thickness of less than approximately 20 Angstroms is formed over the substrate (12). This |
| 5972804 |
Process for forming a semiconductor device |
October 26, 1999 |
| A method for forming an oxynitride gate dielectric layer (202, 204) begins by providing a semiconductor substrate (200). This semiconductor substrate is cleaned via process steps (10-28). Optional nitridation and oxidation are performed via steps (50 and 60) to form a thin interface laye |
| 5580823 |
Process for fabricating a collimated metal layer and contact structure in a semiconductor device |
December 3, 1996 |
| A process for fabricating a semiconductor device which includes forming a collimated metal layer (54) on the surface of a semiconductor substrate (24), while maintaining the temperature of the substrate preferably below about 100.degree. C., and most preferably below about 25.degree. C. |
| 5383354 |
Process for measuring surface topography using atomic force microscopy |
January 24, 1995 |
| Accuracy and repeatability of atomic force microscopy (AFM) are improved by coating a single crystal silicon probe tip with a layer of carbon. The carbon-coated probe tip is brought into contact with a specimen surface, and is scanned across the area of interest. The carbon coating impro |
