| Patent Number |
Title Of Patent |
Date Issued |
| 7288816 |
Semiconductor device |
October 30, 2007 |
| According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction r |
| 7135380 |
Method for manufacturing semiconductor device |
November 14, 2006 |
| In a conventional method for manufacturing a semiconductor device, there are problems that a concave part is formed in a formation region of an isolation region, no flat surface is formed in the isolation region, and a wiring layer is disconnected above the concave part. In a method for |
| 6545337 |
Semiconductor integrated circuit device |
April 8, 2003 |
| Collector regions (32, 33) with films capable of withstanding high voltage by laminating 4 epitaxial layers when the collector regions (32, 33) are formed. In order to reduce effects caused by interference between the transistors (21, 22) and also reduce parasitic transistor, the epitaxi |
| 6528379 |
Method for manufacturing semiconductor integrated circuit device |
March 4, 2003 |
| A buried layer of a collector region and a buried layer of a collector taking-out region are formed at the same time at each epitaxial layer when the collector region and the collector taking-out region of the semiconductor integrated circuit device according to the invention. Each b |
| 6114744 |
Semiconductor integration device and fabrication method of the same |
September 5, 2000 |
| A lead electrode is formed to expose an active base region. A lead electrode for an emitter electrode is formed on the lead electrode in an emitter region, through an insulating film. The insulating film on the lead electrode is then etched to form a contact hole. After that, the emi |
| 6110772 |
Semiconductor integrated circuit and manufacturing method thereof |
August 29, 2000 |
| A semiconductor IC including a resistance element on a circuit substrate. The resistance element includes a resistance layer formed on an insulating layer. The resistance layer is formed using a Si layer obtained by forming an a-Si layer, doping the a-Si layer with impurities, and heatin |
| 6051872 |
Semiconductor integration device and fabrication method of the same |
April 18, 2000 |
| A lead electrode (57) is formed to expose an active base region (61). On the lead electrode (57) is formed a lead electrode (64) for an emitter electrode via an insulation film (56). When a base contact hole (65') for exposing the lead electrode (57) and an emitter contact hole for expos |
