| Patent Number |
Title Of Patent |
Date Issued |
| 7400549 |
Memory block reallocation in a flash memory device |
July 15, 2008 |
| A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline |
| 7372715 |
Architecture and method for NAND flash memory |
May 13, 2008 |
| A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at |
| 7369447 |
Random cache read |
May 6, 2008 |
| A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is us |
| 7345924 |
Programming memory devices |
March 18, 2008 |
| A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the |
| 7324394 |
Single data line sensing scheme for TCCT-based memory cells |
January 29, 2008 |
| A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a de |
| 7269066 |
Programming memory devices |
September 11, 2007 |
| A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the |
| 7196930 |
Flash memory programming to reduce program disturb |
March 27, 2007 |
| The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than V.sub.pass. The memory cells on this unsel |
| 7123521 |
Random cache read |
October 17, 2006 |
| A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is us |
| 7006398 |
Single data line sensing scheme for TCCT-based memory cells |
February 28, 2006 |
| A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a de |
| 6903987 |
Single data line sensing scheme for TCCT-based memory cells |
June 7, 2005 |
| A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a de |
| 6845037 |
Reference cells for TCCT based memory cells |
January 18, 2005 |
| A reference cell produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a TCCT based memory cell in an "on" state. The reference cell includes an NDR device, a gate-like device disposed adjacent to the NDR d |
| 6778435 |
Memory architecture for TCCT-based memory cells |
August 17, 2004 |
| A memory architecture especially adapted to provide an architecture to house one or more TCCT-based memory cells and to provide a reference signal. The memory architecture is designed to effectively resolve stored information from memory cells into logical values, such as logical "0" and |
| 6611452 |
Reference cells for TCCT based memory cells |
August 26, 2003 |
| A reference cell produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a TCCT based memory cell in an "on" state. The reference cell includes an NDR device, a gate-like device disposed adjacent to the NDR d |
| 6130447 |
Integrated circuit memories and power distribution methods including at least two control lines |
October 10, 2000 |
| At least two spaced apart control lines are located between adjacent spaced apart power lines on a memory cell array of an integrated circuit memory device. The spaced apart power lines preferably are wider than the spaced apart control lines, and the space between adjacent control lines |
| 6097649 |
Method and structure for refresh operation with a low voltage of logic high in a memory device |
August 1, 2000 |
| A method and structure for a refresh operation with a low voltage of logic high in a computer memory structure is provided. The method and system includes first the precharging of a plurality of bit lines and a plurality of complementary bit lines to a voltage higher than the reference v |
| 5959924 |
Method and circuit for controlling an isolation gate in a semiconductor memory device |
September 28, 1999 |
| A method of controlling an isolation gate of a semiconductor memory device and a circuit therefor are disclosed. The method includes the steps of generating a refresh row active signal, generating a plurality of block select signals, generating a latch isolation control signal and co |
| 5936896 |
High speed and low power signal line driver and semiconductor memory device using the same |
August 10, 1999 |
| A signal line driver operating at high speed and consuming low power and a semiconductor memory device employing the same are disclosed. The signal line driver includes one or more first pull-up transistors, one or more second pull-up transistors, and one or more pull-down transistors. T |
| 5844857 |
Row address control circuits having a predecoding address sampling pulse generator and methods f |
December 1, 1998 |
| A row address control circuit for a memory device includes a row address enable signal generator, a row address buffer, a row predecoder, a row address strobe buffer, a predecoded row address sampling pulse generator, and a row decoder. The row address enable signal generator produces a |
| 5812466 |
Column redundancy circuit for a semiconductor memory device |
September 22, 1998 |
| The present invention relates to a semiconductor memory device incorporating a column redundancy circuit using a decoded fuse. The column redundancy circuit is capable of designating a repaired address during a parallel test mode of memory operation when an address input is a "don't |
| 5808957 |
Address buffers of semiconductor memory device |
September 15, 1998 |
| Address buffers of a semiconductor memory device have a switching section for switching into each other transmission routes of first and second address signals input from outside in response to predetermined control signals. The signals allow input of the address signals and set the |
| 5784322 |
Standby current detecting circuit for use in a semiconductor memory device and method thereof |
July 21, 1998 |
| A standby current detecting circuit for use in a semiconductor memory device and method thereof are described. The memory device has a plurality of memory cells arranged at crossing points of a plurality of word lines and a plurality of bit lines. A plurality of switches are associated w |
| 5650977 |
Integrated circuit memory device including banks of memory cells and related methods |
July 22, 1997 |
| An integrated circuit memory device includes a plurality of memory cells, a plurality of data lines, a memory cell selector, and a memory cell connector. The memory cells are arranged in a matrix of rows and columns wherein the plurality of memory cells are further grouped in banks with |
| 5640360 |
Address buffer of semiconductor memory device |
June 17, 1997 |
| An address buffer circuit for a semiconductor memory device includes first and second address inputs which are selectably connectable to a first node according to first and second address input control signals, respectively. The device also includes first and second switches which are co |
| 5367491 |
Apparatus for automatically initiating a stress mode of a semiconductor memory device |
November 22, 1994 |
| In a highly integrated semiconductor memory device, apparatus for setting a stress mode without applying a stress voltage from the exterior is provided. A triggered time point T.sub.S to a stress mode can be set by greatly raising an internal supply voltage when the external supply v |
| 5262989 |
Circuit for sensing back-bias level in a semiconductor memory device |
November 16, 1993 |
| A back-bias level sensor used for a semiconductor device wherein a sensing current for sensing a back-bias voltage is prevented from directly flowing into the substrate (or the back-bias voltage terminal). The gate of a PMOS transistor is provided with the back-bias voltage while the sou |
