| Patent Number |
Title Of Patent |
Date Issued |
| 7429787 |
Semiconductor assembly including chip scale package and second substrate with exposed surfaces o |
September 30, 2008 |
| Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second ("land") side, mounted over the molding of the first |
| 7413933 |
Integrated circuit package with leadframe locked encapsulation and method of manufacture therefo |
August 19, 2008 |
| A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connect |
| 7372141 |
Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower side |
May 13, 2008 |
| Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other, that is, the die attach sides of the package |
| 7364945 |
Method of mounting an integrated circuit package in an encapsulant cavity |
April 29, 2008 |
| An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity. |
| 7309913 |
Stacked semiconductor packages |
December 18, 2007 |
| A stacked semiconductor package includes a substrate and a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is |
| 7304859 |
Chip carrier and fabrication method |
December 4, 2007 |
| A substrate having a ground plane, a first side, and a second side is provided. A via that electrically connects the first side to the second side is formed. A printed wire is formed on the first side, and a printed wire is formed on the second side. A passive component is formed on the |
| 7217599 |
Integrated circuit package with leadframe locked encapsulation and method of manufacture therefo |
May 15, 2007 |
| A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connect |
| 7135760 |
Moisture resistant integrated circuit leadframe package |
November 14, 2006 |
| A leadframe for a semiconductor die includes signal leads, ground leads, and a die support holder for supporting the semiconductor die. The die support holder has opposite surfaces and side edges therebetween. The opposite die support holder surfaces are smaller in transverse extent |
| 7091596 |
Semiconductor packages and leadframe assemblies |
August 15, 2006 |
| Semiconductor packages provide a leadframe for packages that are singulated with respective predetermined package body sizes. Individual mold caps are formed on the leadframe with mold cap dimensions that are larger than the respective predetermined package body sizes. The mold caps |
| 7064420 |
Integrated circuit leadframe with ground plane |
June 20, 2006 |
| A leadframe for a semiconductor package includes signal and ground leads, a ground plane, and a frame paddle. Supports connect the signal and ground leads, ground plane, and frame paddle in at least two different layers. At least one force release and stress relief structure is incor |
| 6876069 |
Ground plane for exposed package |
April 5, 2005 |
| A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted. |
| 6861288 |
Stacked semiconductor packages and method for the fabrication thereof |
March 1, 2005 |
| A method for fabricating a stacked semiconductor package includes providing a substrate and mounting a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the subs |
| 6858470 |
Method for fabricating semiconductor packages, and leadframe assemblies for the fabrication ther |
February 22, 2005 |
| A method for fabricating semiconductor packages provides a leadframe for packages that are to be singulated with respective predetermined package body sizes. Individual mold caps are formed on the leadframe with mold cap dimensions that are larger than the respective predetermined packag |
| 6803254 |
Wire bonding method for a semiconductor package |
October 12, 2004 |
| A wire bonding method for electrically interconnecting stacked semiconductor chips is disclosed. A substrate (e.g., printed circuit board or metal leadframe) is provided. Metal circuit patterns are provided outside of a chip mounting region of the substrate, and metal transfer patter |
| 6642610 |
Wire bonding method and semiconductor package manufactured using the same |
November 4, 2003 |
| A semiconductor package including plural semiconductor chips, and a wire bonding step for electrically interconnecting the semiconductor chips, are disclosed. In an exemplary method, a substrate is provided. Conductive circuit patterns are provided outside of a chip mounting region of th |
| 6630373 |
Ground plane for exposed package |
October 7, 2003 |
| A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted. |
| 6489667 |
Semiconductor device and method of manufacturing such device |
December 3, 2002 |
| Semiconductor devices and methods of manufacturing such devices are disclosed. In one embodiment of this invention, a semiconductor chip is bonded to a first surface of a substrate. The substrate extends beyond the edge of the chip. Signal input/output pads on the chip are juxtaposed wit |
| 6462274 |
Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages |
October 8, 2002 |
| Chip-scale semiconductor packages of the fan-out type and methods of manufacturing such packages are disclosed. In one package embodiment within the invention, the package substrate is stiff enough to effectively carry an increased number of solder balls on an exterior area outside the |
| 6414396 |
Package for stacked integrated circuits |
July 2, 2002 |
| Embodiments of integrated circuit packages for housing a plurality of integrated circuits are disclosed, along with methods of making the packages. One integrated circuit package comprises a substrate having a first surface having first metallizations thereon, an opposite second surf |
| 6150709 |
Grid array type lead frame having lead ends in different planes |
November 21, 2000 |
| The invention relates to a grid array type lead frame having a plurality of leads classified into groups by length. The leads extend to respective lead ends, in each of which at least one different plane direction-converting lead part and/or at least one identical plane direction-con |
| 6020219 |
Method of packaging fragile devices with a gel medium confined by a rim member |
February 1, 2000 |
| A fragile device, such as an integrated circuit chip or a multichip assembly, is packaged by first dispensing a sol surrounding the sides of the device. The sol is laterally confined by means of a rim member typically made of a pre-molded plastic material. The amount of the sol dispe |
| 5977624 |
Semiconductor package and assembly for fabricating the same |
November 2, 1999 |
| A chip size semiconductor package with a light, thin, simple and compact structure having a reduced size of its semiconductor chip while having an increased number of pins and without degrading its functions. For the package, it is possible to use either the semiconductor chip having bon |
| 5897334 |
Method for reproducing printed circuit boards for semiconductor packages including poor quality |
April 27, 1999 |
| A method for reproducing a PCB strip for semiconductor packages, wherein a poor quality PCB unit included in the PCB strip is replaced with a normal quality one, thereby achieving a reduction in the amount of package materials used and an improvement in the process efficiency. The invent |
| 5866939 |
Lead end grid array semiconductor package |
February 2, 1999 |
| The invention relates to a grid array type lead frame having a plurality of leads classified into groups by length forming a lead end grid array semiconductor package. The leads extend to respective lead ends, in each of which at least one different plane direction-converting lead part |
| 5858815 |
Semiconductor package and method for fabricating the same |
January 12, 1999 |
| A process for manufacturing chip size semiconductor package with a light, thin, and compact structure having a reduced size of its semiconductor chip while having an increased number of pins For the package, it is possible to use either the semiconductor chip having bond pads arranged on |
| 5834160 |
Method and apparatus for forming fine patterns on printed circuit board |
November 10, 1998 |
| The present inventors have discovered that fine patterns of metal or insulator can be formed on printed circuit board using conventional lithographic steppers with inverted projection lenses. The inverted projection lenses act as enlargement lenses rather than reducing lenses and exh |
| 5767447 |
Electronic device package enclosed by pliant medium laterally confined by a plastic rim member |
June 16, 1998 |
| The bottom and side surfaces of an electronic device, such as an integrated circuit chip or a multichip assembly, are surrounded by a soft gel medium. The gel medium is laterally confined by a rigid plastic rim that is epoxy-bonded in place along its perimeter. A plate, made of plastic o |
| 5646828 |
Thin packaging of multi-chip modules with enhanced thermal/power management |
July 8, 1997 |
| A novel packaging of semiconductor elements, such as MCM tiles, with a variety of printed circuit or wired boards (PWB), the packages occupying a small size, at least in the vertical direction, relative to prior art OMPAC devices. The MCM tile includes an interconnection substrate with |
