| Patent Number |
Title Of Patent |
Date Issued |
| 7358171 |
Method to chemically remove metal impurities from polycide gate sidewalls |
April 15, 2008 |
| An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also relates to a gate |
| 7355244 |
Electrical devices with multi-walled recesses |
April 8, 2008 |
| The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate receptacle that may facilitate a more uniform gate oxide layer. One embodiment relates to a storage cell that is disposed in |
| 7332790 |
Semiconductor device having an active area partially isolated by a lateral cavity |
February 19, 2008 |
| A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep imp |
| 7326960 |
Semiconductor circuit constructions |
February 5, 2008 |
| The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first s |
| 7279725 |
Vertical diode structures |
October 9, 2007 |
| A method of making a vertical diode structure is provided, the vertical diode structure having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode |
| 7276756 |
Memory cell arrays |
October 2, 2007 |
| The invention includes a method of forming an array of memory cells. A series of capacitor constructions is formed, with the individual capacitor constructions having storage nodes. The capacitor constructions are defined to include a first set of capacitor constructions and a second |
| 7273469 |
Modified needle catheter for directional orientation delivery |
September 25, 2007 |
| Methods and apparatus for delivering a treatment agent through a percutaneous delivery apparatus are herein disclosed. In some embodiments, an apparatus can include an expandable body with at least one delivery cannula having a lumen therethrough coupled to an exterior portion of the |
| 7250680 |
Semiconductor circuitry constructions |
July 31, 2007 |
| The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first s |
| 7230312 |
Transistor having vertical junction edge and method of manufacturing the same |
June 12, 2007 |
| Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a heavily doped polysilicon. Ve |
| 7202519 |
Memory cells having an access transistor with a source/drain region coupled to a capacitor throu |
April 10, 2007 |
| Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second |
| 7199017 |
Methods of forming semiconductor circuitry |
April 3, 2007 |
| The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least part |
| 7189662 |
Methods of forming semiconductor constructions |
March 13, 2007 |
| The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor |
| 7179703 |
Method of forming shallow doped junctions having a variable profile gradation of dopants |
February 20, 2007 |
| Disclosed are methods for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. |
| 7170103 |
Wafer with vertical diode structures |
January 30, 2007 |
| A method of making a vertical diode is provided, the vertical diode having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and con |
| 7166875 |
Vertical diode structures |
January 23, 2007 |
| A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and c |
| 7160785 |
Container capacitor structure and method of formation thereof |
January 9, 2007 |
| Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode ("bottom electrodes") of the container capacitor structure. The etch provides a recess between proximal pairs of container |
| 7151041 |
Methods of forming semiconductor circuitry |
December 19, 2006 |
| The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first s |
| 7115957 |
Semiconductor raised source-drain structure |
October 3, 2006 |
| A transistor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate |
| 7115451 |
Methods of forming semiconductor circuitry |
October 3, 2006 |
| The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first s |
| 7098122 |
Method of fabricating a vertically integrated memory cell |
August 29, 2006 |
| A unique cell structure for use in flash memory cell and a method of fabricating the memory cell. More particularly, a vertically integrated transistor having a pair of floating gates is fabricated within a trench in a substrate. The floating gates are fabricated using sidewall spacers |
| 7087468 |
Method for forming conductors in semiconductor devices |
August 8, 2006 |
| A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme |
| 7060599 |
Method of forming shallow doped junctions having a variable profile gradation of dopants |
June 13, 2006 |
| Disclosed is an electrical device having, and a process for forming, a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which t |
| 7045439 |
Methods of forming semiconductor constructions |
May 16, 2006 |
| The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor |
| 7041556 |
Vertical transistor and method of making |
May 9, 2006 |
| The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate receptacle that may facilitate a more uniform gate oxide layer. One embodiment relates to a storage cell that is disposed in |
| 7005710 |
Transistors having controlled conductive spacers, uses of such transistors and methods of making |
February 28, 2006 |
| A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which is contacted and driven separately from the conventional gate of the transistor. The gate spacer, conductive layer of a c |
| 7005692 |
Memory cell arrays |
February 28, 2006 |
| The invention includes a method of forming an array of memory cells. A series of capacitor constructions is formed, with the individual capacitor constructions having storage nodes. The capacitor constructions are defined to include a first set of capacitor constructions and a second |
| 6979631 |
Methods of forming semiconductor circuitry |
December 27, 2005 |
| The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least part |
| 6967132 |
Methods of forming semiconductor circuitry |
November 22, 2005 |
| The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least part |
| 6964896 |
Methods of forming semiconductor logic circuitry, and semiconductor logic circuit constructions |
November 15, 2005 |
| The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first s |
| 6962020 |
Fishing leader holder and method |
November 8, 2005 |
| A fishing leader holder which allows fishermen and fisherwomen to carry leaders of various lengths without the threat of the leaders becoming bent or being caught on other objects. The fishing leader holder (1) is comprised of a holder (1) and two ends (2) and (3) that receive fishing |
| 6958519 |
Methods of forming field effect transistors and field effect transistor circuitry |
October 25, 2005 |
| Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the |
| 6958268 |
Methods of forming memory cell arrays |
October 25, 2005 |
| The invention includes a method of forming an array of memory cells. A series of capacitor constructions is formed, with the individual capacitor constructions having storage nodes. The capacitor constructions are defined to include a first set of capacitor constructions and a second set |
| 6946713 |
Multiple thickness gate dielectric layers |
September 20, 2005 |
| Dual gate dielectric constructions and methods therefor are disclosed for different regions on an integrated circuit. In the illustrated embodiment, gate dielectrics in memory array regions of the chip are formed of silicon oxide, while the gate dielectric in the peripheral region compri |
| 6946173 |
Catheter balloon formed of ePTFE and a diene polymer |
September 20, 2005 |
| A catheter balloon formed of a polymeric material such as expanded polytetrafluoroethylene (ePTFE) bonded to a second layer formed of a low tensile set polymer and/or impregnated with a low tensile set polymer. In a presently preferred embodiment, the low tensile set polymer is a sil |
| 6927431 |
Semiconductor circuit constructions |
August 9, 2005 |
| The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first s |
| 6917083 |
Local ground and VCC connection in an SRAM cell |
July 12, 2005 |
| A retrograde well region, having a buried layer of high conductivity, is formed in a semiconductor substrate. A trench structure is selectively etched in the semiconductor substrate down to a region proximate to or within the buried layer. A conducting local interconnect material is |
| 6908868 |
Gas passivation on nitride encapsulated devices |
June 21, 2005 |
| A method for passivating at least interfaces between structures formed from a conductive or semiconductive material and adjacent dielectric structures so as to reduce a concentration of dangling silicon bonds at these interfaces and to reduce or eliminate the occurrence of unwanted volta |
| 6894310 |
Semiconductor constructions comprising monocrystalline silicon together with semiconductive mate |
May 17, 2005 |
| The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least part |
| 6887753 |
Methods of forming semiconductor circuitry, and semiconductor circuit constructions |
May 3, 2005 |
| The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first s |
| 6882031 |
Ammonia gas passivation on nitride encapsulated devices |
April 19, 2005 |
| A passivation method includes disassociating ammonia so as to expose at least interfaces between silicon-containing and passivation structures to at least hydrogen species derived from the ammonia and forming an encapsulant layer that is positioned so as to substantially contain the |
| 6863757 |
Method of making an expandable medical device formed of a compacted porous polymeric material |
March 8, 2005 |
| A method of making a catheter balloon or other expandable tubular medical device or component thereof formed of a compacted porous polymeric material, in which a tube of porous polymeric material is axially compacted, preferably without increasing the outer diameter of the tube, by p |
| 6861326 |
Methods of forming semiconductor circuitry |
March 1, 2005 |
| The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least part |
| 6855124 |
Flexible polymer needle catheter |
February 15, 2005 |
| A catheter device having an elongated tubular member with a proximal end and a distal end, and a needle disposed near the distal end. In one embodiment, the needle has a rigid, penetrating tip coupled to a flexible portion by an overlapping joint. The flexible portion enables the needle |
| 6844243 |
Methods of forming semiconductor constructions |
January 18, 2005 |
| The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor |
| 6828614 |
Semiconductor constructions, and methods of forming semiconductor constructions |
December 7, 2004 |
| The invention includes an array of devices and a charge pump supported by a semiconductive material substrate. A damage region is under the array, and extends less than or equal to 50% of a distance between the array and the charge pump. The invention also includes a method in which a ma |
| 6800899 |
Vertical transistors, electrical devices containing a vertical transistor, and computer systems |
October 5, 2004 |
| The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate receptacle that may facilitate a more uniform gate oxide layer. One embodiment relates to a storage cell that is disposed in the |
| 6798013 |
Vertically integrated flash memory cell and method of fabricating a vertically integrated flash |
September 28, 2004 |
| A unique cell structure for use in flash memory cell and a method of fabricating the memory cell. More particularly, a vertically integrated transistor having a pair of floating gates is fabricated within a trench in a substrate. The floating gates are fabricated using sidewall spacers |
| 6794239 |
Method of fabrication of semiconductor structures by ion implantation |
September 21, 2004 |
| The present invention relates to the formation of trench isolation structures that isolate active areas and a preferred doping in the fabrication of a CMOS device with a minimized number of masks. Ions of a P-type dopant are implanted into a semiconductor substrate having therein a P |
| 6787401 |
Method of making vertical diode structures |
September 7, 2004 |
| A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and c |
| 6784076 |
Process for making a silicon-on-insulator ledge by implanting ions from silicon source |
August 31, 2004 |
| A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep imp |
