| Patent Number |
Title Of Patent |
Date Issued |
| 7447948 |
ECC coding for high speed implementation |
November 4, 2008 |
| Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detec |
| 7099328 |
Method for automatic resource reservation and communication that facilitates using multiple proc |
August 29, 2006 |
| An integrated circuit for processing communication packets having separate data buffers and separate state information buffers. Each data buffer and each state information buffer (hereinafter termed resources) has an associated in-use counter. Multiple events can share the same resource. |
| 6822959 |
Enhancing performance by pre-fetching and caching data directly in a communication processor's r |
November 23, 2004 |
| Circuitry to free the core processor from performing the explicit read operation required to read data into the internal register set. The processor's register set is expanded and a "shadow register" set is provided. While the core processor is processing one event the "context" and |
| 6760478 |
Method and apparatus for performing two pass quality video compression through pipelining and bu |
July 6, 2004 |
| An apparatus and method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between |
| 6101276 |
Method and apparatus for performing two pass quality video compression through pipelining and bu |
August 8, 2000 |
| An apparatus and method a method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the ta |
| 5638385 |
Fast check bit write for a semiconductor memory |
June 10, 1997 |
| A memory device having an on-chip ECC system includes an array of memory cells, some of which have wider transistors than others so that they have faster access speeds. Data bits are written into ordinary memory cells and the check bits are written into the faster cells in order to make |
| 5532969 |
Clocking circuit with increasing delay as supply voltage VDD |
July 2, 1996 |
| A clocking circuit and clocking method provide a clocking signal that tracks supply voltage VDD such that as supply voltage VDD increases, the signal generation delay also increases. Complementary circuit embodiments and methods are described. In one clocking circuit, a capacitive load |
| 5440258 |
Off-chip driver with voltage regulated predrive |
August 8, 1995 |
| An off-chip driver with regulated supplies compensates for power supply fluctuations. The circuit reduces di/dt noise by providing complementary voltage regulators to regulate the high and low supplies to the driver stages such that they see a constant operating voltage regardless of |
| 5420456 |
ZAG fuse for reduced blow-current application |
May 30, 1995 |
| A fuse, having reduced blow-current requirements thereby minimizing the power supply voltage and chip area required for the driver transistors, has a geometry which is characterized by an essentially uniform width dimension throughout the primary axis of the fuse link but having at least |
| 5418738 |
Low voltage programmable storage element |
May 23, 1995 |
| A programmable storage element for redundancy-programing includes a programmable antifuse circuit, which includes a plurality of first resistors and a switching circuit for coupling the first resistors in series in response to a plurality of first control signals and for coupling the |
| 5412613 |
Memory device having asymmetrical CAS to data input/output mapping and applications thereof |
May 2, 1995 |
| A semiconductor memory chip architecture is described implementing of a multi-bit data control function which enables independent control of at least a plurality of data bits via a single control signal. A logically organized memory chip is organized as a 2.sup.n x 4 chip in which one |
| 5334880 |
Low voltage programmable storage element |
August 2, 1994 |
| A programmable storage element for redundancy-programming includes a programmable antifuse circuit, which includes a plurality of first resistors and a switching circuit for coupling the first resistors in series in response to a plurality of first control signals and for coupling th |
| 5255224 |
Boosted drive system for master/local word line memory architecture |
October 19, 1993 |
| An integrated boost and local word line drive system that enhances the speed of the word line drive without providing excessive voltage stresses to the driver devices. A charge reservoir stores a boost voltage under the control of a charge pump that is regulated by a voltage regulator. O |
| 5221864 |
Stable voltage reference circuit with high Vt devices |
June 22, 1993 |
| A voltage reference circuit that produces an output offset from a supply voltage by approximately two volts, the output being relatively stable in the face of vacillations in the external power supplies. The first leg of the circuit utilizes devices having differing Vt's to produce an in |
