| Patent Number |
Title Of Patent |
Date Issued |
| 7437627 |
Method and test device for determining a repair solution for a memory module |
October 14, 2008 |
| Method for determining a repair solution for a memory module in a test system, memory areas of the memory module being successively tested in order to obtain, for each memory area, a defect datum which specifies whether the respective memory area is defective, wherein defect addresse |
| 7434125 |
Integrated circuit, test system and method for reading out an error datum from the integrated ci |
October 7, 2008 |
| An integrated circuit is provided, the integrated circuit having a test circuit for reading out an error datum from the integrated circuit in accordance with a test mode, wherein the error datum is output via a first and a second data output, and wherein an address and a read command |
| 7427870 |
Test system for testing integrated circuits and a method for configuring a test system |
September 23, 2008 |
| The invention relates to a test system for testing connectable integrated circuits. A particular test system may have switching devices via which a respective assigned one of the integrated circuits can be connected to the supply unit, a control unit for controlling the switching devices |
| 7409308 |
Method and device for verifying output signals of an integrated circuit |
August 5, 2008 |
| A system and method for testing an integrated circuit is provided. In one embodiment, a method includes comparing the signal level of the output signal of the integrated circuit to the signal level of a reference signal, wherein a comparison signal is output, which has a first or a s |
| 7331005 |
Semiconductor circuit device and a system for testing a semiconductor apparatus |
February 12, 2008 |
| Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the testing interface receives test data and a test clock signal from the external test apparatus |
| 7228473 |
Integrated module having a plurality of separate substrates |
June 5, 2007 |
| The invention relates to a module having a first integrated circuit and a second integrated circuit which are arranged on separate substrates, having a first output terminal and a second output terminal to which the first and second integrated circuits are respectfully connected in a |
| 7211451 |
Process for producing a component module |
May 1, 2007 |
| A process for producing a component module comprising a module carrier and a plurality of components with which contact is made on the latter, comprising the following steps: arranging separated components on a surface-adhesive film at a predefined contact-specific spacing from one |
| 7208968 |
Test system for testing integrated chips and an adapter element for a test system |
April 24, 2007 |
| Test system for testing integrated chips and an adapter element for a test system. One embodiment provides a test system for testing integrated chips in a burn-in test operation, the integrated chips to be tested being arranged in groups on a burn-in board, the burn-in board having a |
| 7173473 |
Level-shifting circuitry having "high" output impedance during disable mode |
February 6, 2007 |
| A level shifting circuit includes a level-shifting section responsive to an input logic signal, which varies between a first voltage level (e.g., ground) and a second voltage level (e.g., 2.1V). The level-shifting section provides an output logic signal at an output terminal. The output |
| 7074696 |
Semiconductor circuit module and method for fabricating semiconductor circuit modules |
July 11, 2006 |
| The present invention provides a method for fabricating semiconductor circuit modules having the following steps: application of a patterned connection layer to a transfer substrate, application of active circuit devices and/or passive circuit devices with contact areas pointing toward |
| 7061260 |
Calibration device for the calibration of a tester channel of a tester device and a test system |
June 13, 2006 |
| A calibration device for the calibration of a tester channel of a tester device is provided. The calibration device includes a connecting device and a planar contact carrier with a first contact area and a second contact area insulated from the first contact area, the first contact a |
| 7060529 |
Multiple chip semiconductor arrangement having electrical components in separating regions |
June 13, 2006 |
| A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plu |
| 7034559 |
Integrated test circuit in an integrated circuit |
April 25, 2006 |
| The invention relates to an integrated test circuit in an integrated circuit for testing a plurality of internal voltages. A switching device is provided to select one of the internal voltages in accordance with a selection signal for the purpose of testing, and a comparator device is |
| 6961917 |
Method for activating fuse units in electronic circuit device |
November 1, 2005 |
| The invention provides a method for activating fuse units (101a-101n) in an electronic circuit device (100) in order to modify a circuit design for the electronic circuit device (100), where an electronic circuit device (100) in which fuse units (101a-101n) can be activated is selected, |
| 6961880 |
Recording test information to identify memory cell errors |
November 1, 2005 |
| A method of recording test information to identify a location of errors in Integrated Circuits (ICs) includes scanning a plurality of ICs with an input signal, each IC having a plurality of data locations and comparing an output response at each data location with an expected value for t |
| 6937531 |
Memory device and method of storing fail addresses of a memory cell |
August 30, 2005 |
| The embodiments of the present invention are directed to a self-repair schema for memory chips, using a sortable fail-count/fail-address register. The embodiments of the present invention utilize the available redundancy efficiently by scanning the memory array to locate the n elemen |
| 6909642 |
Self trimming voltage generator |
June 21, 2005 |
| Described are integrated circuit chips that are capable of self-adjusting an internal voltage of the integrated circuit chip and methods for adjusting the internal voltage of an integrated circuit chip. The methods include comparing an internally generated voltage to an external target |
| 6853233 |
Level-shifting circuitry having "high" output impedance during disable mode |
February 8, 2005 |
| A level shifting circuit includes a level-shifting section responsive to an input logic signal, which varies between a first voltage level (e.g., ground) and a second voltage level (e.g., 2.1 V). The level-shifting section provides an output logic signal at an output terminal. The output |
| 6845554 |
Method for connection of circuit units |
January 25, 2005 |
| The invention creates a method for connection of circuit units (101a-10n) which are arranged on a wafer (100), in which the wafer (100) is fitted to a first film (102a), the wafer (100) is sawn such that the circuit units (101a-101n) which are arranged on the wafer (100) are separated, t |
| 6815803 |
Multiple chip semiconductor arrangement having electrical components in separating regions |
November 9, 2004 |
| A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plu |
| 6809972 |
Circuit technique for column redundancy fuse latches |
October 26, 2004 |
| Address information representing failed elements in an array portion of a device is delivered. Respective fail address bit values are stored in a plurality of fuses. A signal associated with a respective value of a portion of a further address is received. When the signal is received, on |
| 6734474 |
Integrated semiconductor circuit having contact points and configuration having at least two suc |
May 11, 2004 |
| For a selection of semiconductor chips stacked on top of one another, the invention includes leading through selection contact points of one chip on a rear side thereof and connecting them to corresponding selection contact points of the other semiconductor chip. Programmable input ampli |
| 6730989 |
Semiconductor package and method |
May 4, 2004 |
| A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plu |
| 6727586 |
Semiconductor component |
April 27, 2004 |
| A semiconductor component that is suitable for wafer level packaging contains a plurality of contact elements that are elevated relative to a main body of the semiconductor component. Some of the contact elements are needed only for purposes of testing on the wafer level and should not b |
| 6717870 |
Method for assessing the quality of a memory unit |
April 6, 2004 |
| Assessing the burn-in of faulty memory units on a wafer includes detecting only those defective memory cells that lie along control lines in the case of which the total number of defective memory cells does not exceed a predetermined limit value. With such a quality criterion, it is also |
| 6714418 |
Method for producing an electronic component having a plurality of chips that are stacked one ab |
March 30, 2004 |
| An electronic component has a plurality of chips which are stacked one above the other and contact-connected to one another. To form this component, a first planar chip arrangement is provided with the functional chips spaced apart from one another in a grid and with a filling material |
| 6707746 |
Fuse programmable I/O organization |
March 16, 2004 |
| Circuitry using fuse and anti-fuse latches (62) for selecting the number of input/output channels (98, 109) after encapsulation is disclosed. The various embodiments allow conventional bond pads (14, 16, 18) to be used for initial selection of the number of input/output channels prior to |
| 6697291 |
Method for checking a conductive connection between contact points |
February 24, 2004 |
| In order to test, in parallel, semiconductor chips formed on a wafer, functionally identical contact points of the semiconductor chips are connected to column lines, and the rows of the semiconductor chips are selected by selection signal lines. This method is suitable in particular |
| 6696319 |
Method of attaching semiconductor devices on a switching device and such an attached device |
February 24, 2004 |
| A method of attaching semiconductor devices, the contact devices of which have preferably already been applied at wafer level, on a switching device and such a device includes having the electrical contacts remain free of solder by using flexible contact elements, and performing the mech |
| 6677770 |
Programmable test socket |
January 13, 2004 |
| A test socket for a semiconductor device includes a guide plate operable to receive the semiconductor device and to maintain electrical terminals of the semiconductor device in registration with electrical terminals of a base, a shell operable to couple to the base and to maintain the gu |
| 6657453 |
Semiconductor wafer testing system and method |
December 2, 2003 |
| An apparatus for testing a plurality of semiconductor devices of a common wafer includes a plurality of driver circuits, each operable to produce an intermediate test signal as a function of a source test signal; a plurality of sets of isolation components, each isolation component of a |
| 6651203 |
On chip programmable data pattern generator for semiconductor memories |
November 18, 2003 |
| A semiconductor memory chip in accordance with the present invention includes a first memory array to be tested including a plurality of memory cells arranged in rows and columns, the memory cells being accessed to read and write data thereto by employing bitlines and wordlines, the data |
| 6649999 |
Semiconductor chip configuration with a layer sequence with functional elements contacted by con |
November 18, 2003 |
| In a semiconductor chip, conductive tracks run in a rewiring layer from contact pads to contact elevations. The contact pads are formed as vias. The conductive tracks are constructed in sections as bottom electrodes of trimming capacitors. The top electrode of the trimming capacitors is |
| 6608783 |
Twisted bit-line compensation |
August 19, 2003 |
| A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being |
| 6603694 |
Dynamic memory refresh circuitry |
August 5, 2003 |
| A circuit for refreshing data stored in an array of dynamic memory cells is provided. The circuit includes an integrated circuit chip. The chip has the array of memory cells formed thereon. The circuit also includes a refresh rate analysis circuit for determining data retention times in |
| 6601205 |
Method to descramble the data mapping in memory circuits |
July 29, 2003 |
| An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes backwards transformation from a given set of logical data patterns. Since the method is automatic, no knowledge of data scrambling in |
| 6580613 |
Solder-free PCB assembly |
June 17, 2003 |
| An electronic component assembly is disclosed. The electronic component assembly may comprise a printed circuit board, a frame secured to the printed circuit board and one or more electronic components mounted in the frame and arranged in electrical contact with conductive traces of the |
| 6570794 |
Twisted bit-line compensation for DRAM having redundancy |
May 27, 2003 |
| A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being |
| 6483764 |
Dynamic DRAM refresh rate adjustment based on cell leakage monitoring |
November 19, 2002 |
| A novel DRAM refresh method and system and a novel method of designing a low-power leakage monitoring device. With the DRAM refresh method, the time is adjusted based directly on the cell leakage condition. The method of designing a low-power leakage monitoring devices uses a memory cell |
| 6426911 |
Area efficient method for programming electrical fuses |
July 30, 2002 |
| A circuit for programming electrical fuses, in accordance with the present invention, includes a shift register including a plurality of latches. Each latch has a corresponding switch and a corresponding electrical fuse. A bit generator generates a single bit of a first state and all oth |
| 6400650 |
Pulse width detection |
June 4, 2002 |
| A semiconductor circuit is provided including circuitry for producing a pulse. A plurality, n, of delay elements are provided each enabled and disabled in parallel by the pulse. Each delay element is adapted to transmit the pulse from an input to an output, with the pulse reaching the |
| 6367027 |
Skew pointer generation |
April 2, 2002 |
| A pointer generation circuit, in accordance with the invention, includes a clock for providing a clock cycle, and a shift register with a plurality of latches for storing data bits. A first latch receives a flag bit upon a first clock cycle of the clock. A switch transfers the flag bit t |
| 6357027 |
On chip data comparator with variable data and compare result compression |
March 12, 2002 |
| A semiconductor memory chip, in accordance with the present invention, includes a memory array including memory components to be tested. A pattern generator provides reference data to be input to and stored in the memory array. A comparator is formed on the memory chip for comparing the |
| 6324125 |
Pulse width detection |
November 27, 2001 |
| A semiconductor circuit is provided including circuitry for producing a pulse. A plurality, n, of delay elements are provided each enabled and disabled in parallel by the pulse. Each delay element is adapted to transmit the pulse from an input to an output, with the pulse reaching the |
| 6262615 |
Dynamic logic circuit |
July 17, 2001 |
| A dynamic logic circuit having a charging circuit, comprising a first transistor having a first source/drain electrode adapted for coupling to a voltage supply and a second source/drain electrode connected to a node. The charging circuit couples the voltage supply to the node to place an |
