| Patent Number |
Title Of Patent |
Date Issued |
| 7411289 |
Integrated circuit package with partially exposed contact pads and process for fabricating the s |
August 12, 2008 |
| A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bonding the semiconduc |
| 7410830 |
Leadless plastic chip carrier and method of fabricating same |
August 12, 2008 |
| A process for fabricating a leadless plastic chip carrier includes providing a leadframe including a plurality of contacts circumscribing a void; fixing a heat sink to the contacts of the leadframe using an intermediate non-electrically conductive adhesive such that the heat sink spa |
| 7372151 |
Ball grid array package and process for manufacturing same |
May 13, 2008 |
| A process for manufacturing an integrated circuit package includes forming a plurality of solder balls on a first surface of a substrate and mounting a semiconductor die to the substrate such that bumps of the semiconductor die are electrically connected to conductive traces of the s |
| 7371610 |
Process for fabricating an integrated circuit package with reduced mold warping |
May 13, 2008 |
| A process for fabricating an integrated circuit package includes mounting a semiconductor die on a first surface of a metal carrier and forming electrical connections between the semiconductor die and ones of a plurality of contacts on the metal carrier. Next, using a molding materia |
| 7315080 |
Ball grid array package that includes a collapsible spacer for separating die adapter from a hea |
January 1, 2008 |
| A ball grid array package is manufactured by mounting a semiconductor die to a first surface of a substrate and mounting a die adapter to the semiconductor die. The semiconductor die is wire bonded to ones of conductive traces of the substrate. A collapsible spacer is mounted to the |
| 7271032 |
Leadless plastic chip carrier with etch back pad singulation |
September 18, 2007 |
| A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, |
| 7270867 |
Leadless plastic chip carrier |
September 18, 2007 |
| A process for fabricating a leadless plastic chip carrier includes selectively depositing a plurality of base layers on a first surface of a base of a leadframe strip to at least partially define a die attach pad and at least one row of contact pads. At least one further layer is sel |
| 7247526 |
Process for fabricating an integrated circuit package |
July 24, 2007 |
| A process for fabricating an integrated circuit package. At least a first side of a leadframe strip is selectively etched to define portions of a die attach pad and at least one row of contacts adjacent the die attach pad. A carrier strip is laminated to the first side of the leadframe |
| 7232755 |
Process for fabricating pad frame and integrated circuit package |
June 19, 2007 |
| A process for fabricating a pad frame for an integrated circuit package includes building up metal on selective portions of a first side of a substrate to define a plurality of contact pads disposed in a first layer of dielectric material, depositing a metal seed layer on an exposed side |
| 7226811 |
Process for fabricating a leadless plastic chip carrier |
June 5, 2007 |
| A process for fabricating a leadless plastic chip carrier includes laminating a first metal strip to a second metal strip to form a leadframe strip, selectively etching the first metal strip to define at least a row of contact pads, mounting a semiconductor die to either a die attach |
| 7091581 |
Integrated circuit package and process for fabricating the same |
August 15, 2006 |
| A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bonding the semiconduc |
| 7081403 |
Thin leadless plastic chip carrier |
July 25, 2006 |
| A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe strip using a mask, follows selectively etching, to provide exposed areas of the surface at |
| 7049177 |
Leadless plastic chip carrier with standoff contacts and die attach pad |
May 23, 2006 |
| A process for fabricating a leadless plastic chip carrier includes selectively etching at least a first surface of a leadframe strip to partially define at least a plurality of contact pads and a die attach pad; selectively plating at least one layer of metal on a second surface of t |
| 7033517 |
Method of fabricating a leadless plastic chip carrier |
April 25, 2006 |
| A leadless plastic chip carrier is fabricated by partially etching at least a first surface of a leadframe strip to partially define a die attach pad, a plurality of contact pads disposed around the die attach pad, and a plurality of bond fingers intermediate the die attach pad and t |
| 7015072 |
Method of manufacturing an enhanced thermal dissipation integrated circuit package |
March 21, 2006 |
| In one aspect, the present invention relates to a method of manufacturing an integrated circuit package, the method including installing a carrier onto a substrate, attaching a semiconductor die to the substrate, and aligning an assembly over the semiconductor die, wherein the assembly |
| 7009286 |
Thin leadless plastic chip carrier |
March 7, 2006 |
| A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe strip using a mask, follows selectively etching, to provide exposed areas of the surface at |
| 6995460 |
Leadless plastic chip carrier with etch back pad singulation |
February 7, 2006 |
| A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, |
| 6989294 |
Leadless plastic chip carrier with etch back pad singulation |
January 24, 2006 |
| A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, |
| 6987032 |
Ball grid array package and process for manufacturing same |
January 17, 2006 |
| A ball grid array package is manufactured by mounting a semiconductor die to a first surface of a substrate and mounting a die adapter to the semiconductor die. The semiconductor die is wire bonded to ones of conductive traces of the substrate. A collapsible spacer is mounted to the |
| 6982491 |
Sensor semiconductor package and method of manufacturing the same |
January 3, 2006 |
| A process for fabricating an integrated circuit package includes: providing a substrate having conductive traces therein, the substrate including a cavity therein; mounting a semiconductor die to a first surface of the substrate, in a flip-chip orientation such that a sensor portion |
| 6979594 |
Process for manufacturing ball grid array package |
December 27, 2005 |
| A ball grid array package is manufactured by mounting a semiconductor die to a first surface of a substrate array. Wires are bonded between the semiconductor die and ones of conductive traces of the substrate array. The heat spreader is disposed in a mold and the substrate array is r |
| 6964918 |
Electronic components such as thin array plastic packages and process for fabricating same |
November 15, 2005 |
| A process for fabricating an integrated circuit package includes establishing a plating mask on a first surface of a metal carrier. The plating mask defines a plurality of components including a die attach pad, at least one row of contact pads and at least one additional electronic c |
| 6946324 |
Process for fabricating a leadless plastic chip carrier |
September 20, 2005 |
| A process for fabricating a leadless plastic chip carrier includes laminating a first metal strip to a second metal strip to form a leadframe strip, selectively etching the first metal strip to define at least a row of contact pads, mounting a semiconductor die to either a die attach pad |
| 6933594 |
Leadless plastic chip carrier with etch back pad singulation |
August 23, 2005 |
| A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, |
| 6933176 |
Ball grid array package and process for manufacturing same |
August 23, 2005 |
| A ball grid array integrated circuit package is manufactured by mounting a semiconductor die, to a surface of a substrate such that bumps on the semiconductor die are electrically connected to conductive traces of the substrate. At least one collapsible spacer is mounted to at least one |
| 6903304 |
Process for dressing molded array package saw blade |
June 7, 2005 |
| A process for reworking or dressing a saw blade used in wafer dicing and singulation of molded array integrated circuit packages, includes rotating the saw blade on a spindle and ablating an edge portion of the saw blade using a laser and thereby dressing the saw blade. |
| 6872661 |
Leadless plastic chip carrier with etch back pad singulation and die attach pad array |
March 29, 2005 |
| A leadless plastic chip carrier has a plurality of die attach pads on which a singulated semi-conductor die is mounted. At least one row of contact pads circumscribes the plurality of die attach pads and a power/ground ring is intermediate the contact pads and the die attach pads. Wire b |
| 6818978 |
Ball grid array package with shielding |
November 16, 2004 |
| An integrated circuit package is provided. The package has a substrate having first and second surfaces and a plurality of conductive traces therebetween. A stacked semiconductor die apparatus is coupled to the substrate. The stacked semiconductor die apparatus includes a first semic |
| 6818472 |
Ball grid array package |
November 16, 2004 |
| An integrated circuit package including a substrate having opposing first and second surfaces. The substrate has conductive traces disposed therein. A semiconductor die is mounted on the first surface of the substrate and a silicon heat sink disposed on a portion of the semiconductor die |
| 6800948 |
Ball grid array package |
October 5, 2004 |
| An integrated circuit package including a substrate having opposing first and second surfaces. The substrate has conductive traces disposed therein. A semiconductor die is mounted on the first surface of the substrate and a silicon heat sink disposed on a portion of the semiconductor die |
| 6790710 |
Method of manufacturing an integrated circuit package |
September 14, 2004 |
| In one aspect, the present invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive |
| 6781242 |
Thin ball grid array package |
August 24, 2004 |
| An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. The substrate further has a cavity therein and a heat slug is fixed to the substrate and spans the cavity. A semiconductor die i |
| 6734552 |
Enhanced thermal dissipation integrated circuit package |
May 11, 2004 |
| In one aspect, the present invention relates to an integrated circuit package includes a scmiconductor die electrically connected to a substrate, a heat sink having a top and a side portion, the heat sink further including an extending finger when viewed from a top of the package, th |
| 6734044 |
Multiple leadframe laminated IC package |
May 11, 2004 |
| A method of fabricating an integrated circuit package. The method includes providing a first leadframe and a second leadframe, laminating the second leadframe to a portion of the first leadframe in order to create a multi-layer laminated leadframe, and mounting a semiconductor die on |
| 6635957 |
Leadless plastic chip carrier with etch back pad singulation and die attach pad array |
October 21, 2003 |
| A leadless plastic chip carrier has a plurality of die attach pads on which a singulated semi-conductor die is mounted. At least one row of contact pads circumscribes the plurality of die attach pads and a power/ground ring is intermediate the contact pads and the die attach pads. Wire b |
| 6585905 |
Leadless plastic chip carrier with partial etch die attach pad |
July 1, 2003 |
| A leadless plastic chip carrier comprising a die attach pad, a semiconductor die mounted to a portion of the die attach pad and at least one row of contact pads circumscribing the die attach pad. The row of contact pads have a thickness greater than the thickness of the portion of th |
| 6429048 |
Metal foil laminated IC package |
August 6, 2002 |
| A method of fabricating an integrated circuit package for ball grid arrays, comprising the steps of: laminating layers of fiberglass prepreg and copper foil to a copper plate in order to create a three-layer laminated carrier; patterning and etching contact pads for input/output and a |
