| Patent Number |
Title Of Patent |
Date Issued |
| 7184468 |
Method and system for implementing a conditional one's complement of partial address |
February 27, 2007 |
| Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the seq |
| 7177988 |
Method and system for synchronizing processor and DMA using ownership flags |
February 13, 2007 |
| Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the seq |
| 7146391 |
Method and system for implementing SLICE instructions |
December 5, 2006 |
| Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the seq |
| 7142139 |
Powering down of DAC and ADC for receive/transmit modes of operation in a wireless device |
November 28, 2006 |
| A digital-to-analog converter (DAC) disposed in a data transmission path to convert data from a digital format to an analog format to be transmitted is powered down during a receive mode of operation for a wireless communication device. Likewise, an analog-to-digital converter (ADC) |
| 7116259 |
Switching between lower and higher power modes in an ADC for lower/higher precision operations |
October 3, 2006 |
| An analog-to-digital converter (ADC) disposed in a data reception path to convert data from an analog format to a digital format is switched between two or more power modes to conserve power when data is not being received. ADC stays in a lower power-lower precision mode until an inb |
| 7079058 |
Powering down of DAC and ADC for receive/transmit modes of operation in a wireless device |
July 18, 2006 |
| A digital-to-analog converter (DAC) disposed in a data transmission path to convert data from a digital format to an analog format to be transmitted is powered down during a receive mode of operation for a wireless communication device. Likewise, an analog-to-digital converter (ADC) |
| 6721878 |
Low-latency interrupt handling during memory access delay periods in microprocessors |
April 13, 2004 |
| A method and processor configured to handle an exception may employ a "retry" signal, which may be associated with a memory access attempt by the processor. The retry signal determines if an exception is to be serviced during a period in which the memory access is delayed. In one emb |
| 6704863 |
Low-latency DMA handling in pipelined processors |
March 9, 2004 |
| A method, system and processor are provided for minimizing latency and loss of processor bandwidth in a pipelined processor when responding to an interrupt. The method advantageously avoids emptying and refilling the processor's instruction pipeline in order to service an interrupt reque |
