| Patent Number |
Title Of Patent |
Date Issued |
| 6094715 |
SIMD/MIMD processing synchronization |
July 25, 2000 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are |
| 5966528 |
SIMD/MIMD array processor with vector processing |
October 12, 1999 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are |
| 5963746 |
Fully distributed processing memory element |
October 5, 1999 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are |
| 5963745 |
APAP I/O programmable router |
October 5, 1999 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processor memory elements on a single chip have their own associated processing element, significant memory, a |
| 5878241 |
Partitioning of processing elements in a SIMD/MIMD array processor |
March 2, 1999 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are |
| 5870619 |
Array processor with asynchronous availability of a next SIMD instruction |
February 9, 1999 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are |
| 5842031 |
Advanced parallel array processor (APAP) |
November 24, 1998 |
| A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor m |
| 5828894 |
Array processor having grouping of SIMD pickets |
October 27, 1998 |
| Array processors are made by assembling individual microcomputer elements into an array. Larger arrays are called massively parallel processors. Some can operate in SIMD, while others can operate in MIMD, or SIMD and MIMD in special configurations. In a SIMD array of processors, there is |
| 5822608 |
Associative parallel processing system |
October 13, 1998 |
| Multiprocessor parallel computing systems and a byte serial SIMD processor parallel architecture is used for parallel array processing with a simplified architecture adaptable to chip implementation in an air cooled environment. The array provided is an N dimensional array of byte wide |
| 5815723 |
Picket autonomy on a SIMD machine |
September 29, 1998 |
| A parallel array computer provides an array of processor memory elements interconnected for transfer of data and instructions between processor memory elements. Each of the processing elements has a processor coupled with a local memory. An array controller is provided for controlling th |
| 5809292 |
Floating point for simid array machine |
September 15, 1998 |
| A floating point system and method according to a format that includes a sign bit, an exponent part having a plurality of bits, and a fraction part having a plurality of multi-bit blocks, wherein floating point operation is based on block shifts of the fraction part, with each shift of o |
| 5805915 |
SIMIMD array processing system |
September 8, 1998 |
| A conventional SIMD processor array architecture's functions are amplified by a SIMIMD architecture where more programmable flexibility would be useful. Decision making in general and specifically classification where decision trees are common, is a problem eased by SIMIMD. A SIMD array |
| 5794059 |
N-dimensional modified hypercube |
August 11, 1998 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAWM processing while incorporating processing elements on a single chip, with nodes connected in an n-dimensional modified non-binary hypercube. In a 4-dimensional modified non-binary |
| 5765015 |
Slide network for an array processor |
June 9, 1998 |
| In arrays of processors, especially linear arrays, it is important to be able to communicate to adjacent neighbors (en masse). That is, each element of the array can communicate with its neighbor on the left simultaneously. In addition, the array processor is provided with the abilit |
| 5765012 |
Controller for a SIMD/MIMD array having an instruction sequencer utilizing a canned routine libr |
June 9, 1998 |
| A controller for a SIMD processor array that can execute instructions within each processing element is described. This three stage hierarchical controller executes instructions at the function, routine, and micro-level, to maximize the effectiveness of processing within the array el |
| 5765011 |
Parallel processing system having a synchronous SIMD processing with processing elements emulati |
June 9, 1998 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are |
| 5761523 |
Parallel processing system having asynchronous SIMD processing and data parallel coding |
June 2, 1998 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are |
| 5754871 |
Parallel processing system having asynchronous SIMD processing |
May 19, 1998 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are |
| 5752067 |
Fully scalable parallel processing system having asynchronous SIMD processing |
May 12, 1998 |
| Parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are |
| 5734921 |
Advanced parallel array processor computer package |
March 31, 1998 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are |
| 5717944 |
Autonomous SIMD/MIMD processor memory elements |
February 10, 1998 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are |
| 5717943 |
Advanced parallel array processor (APAP) |
February 10, 1998 |
| A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor m |
| 5713037 |
Slide bus communication functions for SIMD/MIMD array processor |
January 27, 1998 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are |
| 5710935 |
Advanced parallel array processor (APAP) |
January 20, 1998 |
| A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor m |
| 5708836 |
SIMD/MIMD inter-processor communication |
January 13, 1998 |
| A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are |
