| Patent Number |
Title Of Patent |
Date Issued |
| RE31083 |
Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or M |
November 16, 1982 |
| New non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structures are described. With the graded or stepped insulator, electrons or holes can be injected from the gate electrode at low to moderate applied fields. The carriers flow under the |
| 5617351 |
Three-dimensional direct-write EEPROM arrays and fabrication methods |
April 1, 1997 |
| A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A |
| 5468663 |
Method of fabricating three-dimensional direct-write EEPROM arrays |
November 21, 1995 |
| A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A |
| 5467305 |
Three-dimensional direct-write EEPROM arrays and fabrication methods |
November 14, 1995 |
| A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A |
| 4939559 |
Dual electron injector structures using a conductive oxide between injectors |
July 3, 1990 |
| The present invention relates to DEIS (Dual Electron Injector Structure) EAROM (Electrically Alterable Read Only Memory) devices which utilize a silicon-rich, silicon dioxide insulator between injectors which has an excess of silicon therein which is less than the excess of silicon in th |
| 4752812 |
Permeable-base transistor |
June 21, 1988 |
| A semiconductor structure that includes a semiconductor substrate; an insulating layer adjacent the substrate; a semiconductor or conductor grid adjacent the insulating layer; another insulating layer adjacent the semiconductor grid; and an injector adjacent the second insulating layer. |
| 4662719 |
Liquid crystal display and method for production |
May 5, 1987 |
| A matrix addressable liquid crystal display includes a thin film circuit supported on a substrate having a plurality of parallel bit lines. A plurality of individual pixel circuits each include a two terminal bi-directional gate device which is formed from at least one thin film laye |
| 4472726 |
Two carrier dual injector apparatus |
September 18, 1984 |
| A two carrier dual injector semiconductor apparatus utilizing a pair of injector gates for simultaneously injecting holes and electrons into a series stack of insulator layers. The stacked insulator layers which may be arranged in a MIM or MIS configuration have injecting layers near |
| 4471471 |
Non-volatile RAM device |
September 11, 1984 |
| Juxtaposing, on a common p-type substrate, an array of field effect transistor memory cells each including a random access memory dynamic RAM device comprising a floating gate portion and a storage node, and each including also a non-volatile unit comprising a double electron injector |
| 4432072 |
Non-volatile dynamic RAM cell |
February 14, 1984 |
| This invention provides improved non-volatile semiconductor memories which include a one device dynamic volatile memory circuit having a switching device, a storage capacitor and a non-volatile floating gate device disposed between the storage node and the switching device. The non-v |
| 4217601 |
Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or M |
August 12, 1980 |
| New non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structures are described. With the graded or stepped insulator, electrons or holes can be injected from the gate electrode at low to moderate applied fields. The carriers flow under the |
| 4143393 |
High field capacitor structure employing a carrier trapping region |
March 6, 1979 |
| A high field capacitor structure includes an insulating layer having a carrier trapping region between two electrodes. The trapping region improves electric breakdown characteristics of the capacitor structure and is particularly useful in avoiding the low breakdown voltages and high |
| 4104675 |
Moderate field hole and electron injection from one interface of MIM or MIS structures |
August 1, 1978 |
| A graded oxide MIM or MIS structure employs band gap grading of the insulator oxide so that holes or electrons (depending on voltage bias) can be injected into the insulator oxide under moderate electric field conditions from the contact at one interface. Electron or hole injection f |
