| Patent Number |
Title Of Patent |
Date Issued |
| 6632689 |
Method for processing semiconductor wafers in an enclosure with a treated interior surface |
October 14, 2003 |
| A process for manufacturing semiconductors uses an enclosure (22) having an interior surface-that is intentionally-roughened by spraying quartz (44) onto the interior surface. The sprayed quartz (44) creates additional surface area for the purpose of trapping or capturing etched material |
| 6500315 |
Method and apparatus for forming a layer on a substrate |
December 31, 2002 |
| A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate (901) is placed into a chamber (30) that includes a coil (16) and a shield (14) wherein the coil and the shield are electrically isolated by an isolation/support mem |
| 6476623 |
Percent backsputtering as a control parameter for metallization |
November 5, 2002 |
| A method for depositing a first metal layer such as tantalum or copper on a patterned semiconductor wafer using a metal sputtering tool that typically includes an electrically biased wafer chuck is disclosed. Initially, a first test wafer is placed on the wafer chuck and a first test lay |
| 6451181 |
Method of forming a semiconductor device barrier layer |
September 17, 2002 |
| A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not s |
| 6294458 |
Semiconductor device adhesive layer structure and process for forming structure |
September 25, 2001 |
| The formation of an adhesion/interlayer region (410) of a semiconductor substrate device (404) before barrier layer (412) deposition provides improved adhesion of the barrier layer (412) to the underlying dielectric (404) and increases strength to the next interconnect layer without |
| 6218302 |
Method for forming a semiconductor device |
April 17, 2001 |
| An interconnect (60) is formed overlying a substrate (10). In one embodiment, an adhesion/barrier layer (81), a copper-alloy seed layer (42), and a copper film (43) are deposited overlying the substrate (10), and the substrate (10) is annealed. In an alternate embodiment, a copper fi |
| 6187682 |
Inert plasma gas surface cleaning process performed insitu with physical vapor deposition (PVD) |
February 13, 2001 |
| A method for insitu performing a cleaning operation along with a physical sputtering operation begins by placing a wafer (26) into a chamber (12). A plasma (30) is generated within the chamber (12) using an inert, noble, or reducing gas. The gas is ionized to form ions (32) within the pl |
| 6139696 |
Method and apparatus for forming a layer on a substrate |
October 31, 2000 |
| A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate (901) is placed into a chamber (30) that includes a coil (16) and a shield (14) wherein the coil and the shield are electrically isolated by an isolation/support mem |
| 6136682 |
Method for forming a conductive structure having a composite or amorphous barrier layer |
October 24, 2000 |
| A method for forming an improved copper barrier layer begins by providing a silicon-containing layer (10). A physical vapor deposition process is then used to form a thin tantalum nitride amorphous layer (12). A thin amorphous titanium nitride layer (14) is then deposited over the amorph |
| 5958508 |
Process for forming a semiconductor device |
September 28, 1999 |
| A metal-semiconductor layer (26) is formed over an insulating layer (20) such that the metal-semiconductor layer (26) is graded to have varying amounts of the semiconductor and metal throughout the layer. In one embodiment, the metal-semiconductor layer (26) has relatively higher sil |
| 5893752 |
Process for forming a semiconductor device |
April 13, 1999 |
| A semiconductor device comprises a substrate (100), first conductive film (22 and 32) over the substrate (100), and a second conductive film (54 and 64) over the first conductive film (22 and 32). The first conductive film includes a refractory metal and nitrogen. The first conductive fi |
| 5308788 |
Temperature controlled process for the epitaxial growth of a film of material |
May 3, 1994 |
| A ramp activated low temperature quality epitaxial growth process. A substrate is pre-conditioned and a passivation layer overlying the substrate surface is formed. The substrate is introduced into a process chamber having a controlled temperature. A process chamber purge technique i |
