| Patent Number |
Title Of Patent |
Date Issued |
| 7372158 |
HDP-based ILD capping layer |
May 13, 2008 |
| A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si--C--H compound disposed over the first layer. The |
| 7326651 |
Method for forming damascene structure utilizing planarizing material coupled with compressive d |
February 5, 2008 |
| This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive d |
| 7179760 |
Bilayer cap structure including HDP/bHDP films for conductive metallization and method of making |
February 20, 2007 |
| The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition p |
| 7138717 |
HDP-based ILD capping layer |
November 21, 2006 |
| A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si--C--H compound disposed over the first layer. The |
| 7084079 |
Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane |
August 1, 2006 |
| A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor |
| 6946345 |
Self-aligned buried strap process using doped HDP oxide |
September 20, 2005 |
| The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive b |
| 6911378 |
Stabilization of fluorine-containing dielectric materials in a metal insulator wiring structure |
June 28, 2005 |
| A process for providing regions of substantially lower fluorine content in a fluorine-containing dielectric comprises exposing the fluorine-containing dielectric to a reactive species to form volatile byproducts. |
| 6740539 |
Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates |
May 25, 2004 |
| A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less |
| 6667504 |
Self-aligned buried strap process using doped HDP oxide |
December 23, 2003 |
| The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive b |
| 6570256 |
Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates |
May 27, 2003 |
| A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less |
| 6548357 |
Modified gate processing for optimized definition of array and logic devices on same chip |
April 15, 2003 |
| Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is ma |
| 6531412 |
Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane |
March 11, 2003 |
| A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such |
| 6500772 |
Methods and materials for depositing films on semiconductor substrates |
December 31, 2002 |
| A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R--NH).sub.4-n SiX.sub.n, wherein R is an alkyl group, n is 1, 2, or 3, an |
| 6486015 |
Low temperature carbon rich oxy-nitride for improved RIE selectivity |
November 26, 2002 |
| Reactive ion etch (RIE) selectivity during etching of a feature nearby embedded structure is improved by using a silicon oxynitride layer formed with carbonization throughout layer. |
| 6429149 |
Low temperature LPCVD PSG/BPSG process |
August 6, 2002 |
| A disclosed process use low pressure chemical vapor deposition (LPCVD) of doped oxide film on a substrate. The process includes the steps of providing a substrate in an LPCVD reactor and flowing BTBAS and oxygen into the LPCVD reactor to react on the substrate to deposit an oxide film |
| 6403423 |
Modified gate processing for optimized definition of array and logic devices on same chip |
June 11, 2002 |
| Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is ma |
| 6335261 |
Directional CVD process with optimized etchback |
January 1, 2002 |
| A method is described for filling a high-aspect-ratio feature, in which compatible deposition and etching steps are performed in a sequence. The feature is formed as an opening in a substrate having a surface; a fill material is deposited at the bottom of the feature and on the surface o |
| 6274440 |
Manufacturing of cavity fuses on gate conductor level |
August 14, 2001 |
| A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electri |
| 6232222 |
Method of eliminating a critical mask using a blockout mask and a resulting semiconductor struct |
May 15, 2001 |
| A method of forming a semiconductor structure may include forming a semiconductor substrate having an array region and a support region, forming a semiconductor substrate and a gate stack over the support region of the substrate and applying a critical mask over the support region and |
| 6208008 |
Integrated circuits having reduced stress in metallization |
March 27, 2001 |
| The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the |
| 6177344 |
BPSG reflow method to reduce thermal budget for next generation device including heating in a st |
January 23, 2001 |
| A multistep method for planarizing a silicon oxide insulating layer such as a deposited borophosphosilicate glass (BPSG) layer. The method includes several different planarization stages. During an initial, pre-planarization stage, a substrate having a BPSG layer deposited over it is |
| 6159870 |
Borophosphosilicate glass incorporated with fluorine for low thermal budget gap fill |
December 12, 2000 |
| A method of depositing a fluorinated borophosphosilicate glass (FBPSG) on a semiconductor device as either a final or interlayer dielectric film. Gaps having aspect ratios greater than 6:1 are filled with a substantially void-free FBPSG film at a temperature of about 480.degree. C. at |
| 6077786 |
Methods and apparatus for filling high aspect ratio structures with silicate glass |
June 20, 2000 |
| Filling of narrow and/or high aspect ratio gaps and trenches with silicate glass is accomplished at reduced temperatures and without reflow by etching the glass concurrently with thermal chemical vapor deposition of the glass such that the deposition rate will exceed the etching rate by |
| 6030881 |
High throughput chemical vapor deposition process capable of filling high aspect ratio structure |
February 29, 2000 |
| A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and etch steps having varying etch rate-to-deposition rate (etch/dep) ratios. The first step uses an etch/dep ratio les |
| 5939335 |
Method for reducing stress in the metallization of an integrated circuit |
August 17, 1999 |
| The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the |
| 5614247 |
Apparatus for chemical vapor deposition of aluminum oxide |
March 25, 1997 |
| An apparatus in a chemical vapor deposition (CVD) system monitors the actual wafer/substrate temperature during the deposition process. The apparatus makes possible the production of high quality aluminum oxide films with real-time wafer/substrate control. An infrared (IR) temperature |
| 5540777 |
Aluminum oxide LPCVD system |
July 30, 1996 |
| A process and apparatus for Al.sub.2 O.sub.3 CVD on silicon wafers using aluminum tri-isopropoxide in a high-volume production environment is presented. The conditions required to use ATI in a production environment and provide maximum utilization of ATI are first of all delivery of ATI |
| 5534066 |
Fluid delivery apparatus having an infrared feedline sensor |
July 9, 1996 |
| An apparatus for processing a layer on a workpiece includes a source of reactant fluid, a reaction chamber having a support for the workpiece and a fluid delivery apparatus for feeding an input fluid into the reaction chamber with the input fluid being utilized to process the material. A |
| 5492718 |
Fluid delivery apparatus and method having an infrared feedline sensor |
February 20, 1996 |
| An apparatus for processing a layer on a workpiece includes a source of reactant fluid, a reaction chamber having a support for the workpiece and a fluid delivery apparatus for feeding an input fluid into the reaction chamber with the input fluid being utilized to process the material. A |
| 5431734 |
Aluminum oxide low pressure chemical vapor deposition (LPCVD) system-fourier transform infrared |
July 11, 1995 |
| A method and apparatus for monitoring and controlling reactant vapors prior to chemical vapor deposition (CVD). The reactant vapors are monitored at full concentration without sampling as they are transported to a CVD reactor. Contaminants detected cause a process controller to switch th |
| 5425810 |
Removable gas injectors for use in chemical vapor deposition of aluminium oxide |
June 20, 1995 |
| A removable gas injector design compatible for use in chemical vapor deposition reactors that allows proper mixing of the reactant gases, reduced cycle time associated with cleaning of gas injector components, and elimination of uncertainties associated with manual cleaning of the in |
| 5383088 |
Storage capacitor with a conducting oxide electrode for metal-oxide dielectrics |
January 17, 1995 |
| A capacitor having a high dielectric constant and method of making the same is disclosed. The capacitor comprises a bottom electrode comprising a conductive oxide deposited upon a substrate by chemical vapor deposition. A dielectric layer having a high dielectric constant is deposited up |
| 5328868 |
Method of forming metal connections |
July 12, 1994 |
| A metal connection for an integrated circuit device is effectively "cast" in place at any level of an integrated circuit. The "mold" for the connection is formed by depositing and patterning a sacrificial material, such as aluminum oxide or other metal oxides, and covering the sacrificia |
| 5268069 |
Safe method for etching silicon dioxide |
December 7, 1993 |
| Anhydrous ammonium fluoride is used as a safe source of hydrogen fluoride for etching native or other silicon dioxide layers from silicon substrates. Heating the anhydrous ammonium fluoride above its sublimation temperature results in the generation of hydrogen fluoride gas which etc |
| 5134963 |
LPCVD reactor for high efficiency, high uniformity deposition |
August 4, 1992 |
| An injector with a convex wall surface facing the susceptor directs vapor toward a wafer held by a susceptor producing a generally laminar flow across the surface of the wafer that in combination with the convex wall surface prevents formation of recirculation cells in the region between |
