| Patent Number |
Title Of Patent |
Date Issued |
| RE37305 |
Virtual memory address translation mechanism with controlled data persistence |
July 31, 2001 |
| A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory functions such as journalling. Th |
| 5805832 |
System for parametric text to text language translation |
September 8, 1998 |
| The present invention is a system for translating text from a first source language into a second target language. The system assigns probabilities or scores to various target-language translations and then displays or makes otherwise available the highest scoring translations. The sourc |
| 5768603 |
Method and system for natural language translation |
June 16, 1998 |
| The present invention is a system for translating text from a first source language into a second target language. The system assigns probabilities or scores to various target-language translations and then displays or makes otherwise available the highest scoring translations. The sourc |
| 5477451 |
Method and system for natural language translation |
December 19, 1995 |
| The present invention is a system for translating text from a first source language into a second target language. The system assigns probabilities or scores to various target-language translations and then displays or makes otherwise available the highest scoring translations. The sourc |
| 4992938 |
Instruction control mechanism for a computing system with register renaming, map table and queue |
February 12, 1991 |
| A floating point instruction control mechanism which processes loads and stores in parallel with arithmetic instructions. This results from register renaming, which removes output dependencies in the instruction control mechanism and allows computations aliased to the same register to |
| 4969118 |
Floating point unit for calculating A=XY+Z having simultaneous multiply and add |
November 6, 1990 |
| A single floating point that produces the result A.times.B+C with A, B and C being floating point numbers. The operand C is shifted in parallel with the beginning phases of the multiplication. The result is produced after a single addition and normalization, reducing hardware, delay and |
| 4937736 |
Memory controller for protected memory with automatic access granting capability |
June 26, 1990 |
| A method and apparatus for controlling access to data blocks stored by addresses in a memory and concurrently accessible by a plurality of transactions is provided. The method includes the steps of receiving an address of a data block to be accessed by a first transaction, deriving f |
| 4802091 |
Method for improving the efficiency of arithmetic code generation in an optimizing compiler usin |
January 31, 1989 |
| A procedure for use in an optimizing compiler termed "reassociation" determines the preferred order of combining terms in a sum so as to produce loop invariant subcomputations, or to promote common subexpressions among several essential computations, by applying the associative law o |
| 4719568 |
Hierarchical memory system including separate cache memories for storing data and instructions |
January 12, 1988 |
| A hierarchical memory system for use with a high speed data processor characterized by having separate dedicated cache memories for storing data and instructions and further characterized by each cache having a unique cache directory containing a plurality of control bits for assisting l |
| 4710868 |
Interconnect scheme for shared memory local networks |
December 1, 1987 |
| A plurality of intelligent work stations are provided access to a shared memory through a switching hierarchy including a first array of mapping boxes for receiving a first address from an intelligent work station and including a virtual address and offset and for converting the virtual |
| 4656583 |
Method for improving global common subexpression elimination and code motion in an optimizing co |
April 7, 1987 |
| A method for use during the optimizatin phase of an optimizing compiler for performing global common subexpression elimination and code motion which comprises:Determining the code `basis` for the object program which includes examining each basic block of code and determining the `basis` |
| 4642765 |
Optimization of range checking |
February 10, 1987 |
| A method operable within an optimizing compiler to move certain range check instructions out of single entry strongly connected regions or loops and into linear regions of the instruction stream whereby computational efficiency is increased with no loss of program accuracy. The method |
| 4638426 |
Virtual memory address translation mechanism with controlled data persistence |
January 20, 1987 |
| A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory functions such as journalling. Th |
| 4589087 |
Condition register architecture for a primitive instruction set machine |
May 13, 1986 |
| A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not |
| 4589065 |
Mechanism for implementing one machine cycle executable trap instructions in a primitive instruc |
May 13, 1986 |
| A mechanism for performing a run-time storage address validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its func |
| 4587579 |
System for position detection on a rotating disk |
May 6, 1986 |
| An information reading/writing head is positioned to follow data tracks that are formed concentrically on a magnetic recording disk. A set of spiral radial position-indicating markings if formed which can be detected on the disk optically, or capacitively. The position of the head is |
| 4564944 |
Error correcting scheme |
January 14, 1986 |
| A method and an apparatus are disclosed for converting error syndromes of an error-correcting code to pointers which identify the positions of the erroneous bits. Each syndrome is converted by a plurality of hashing functions into a plurality of hash words, which in turn are used to |
| 4306286 |
Logic simulation machine |
December 15, 1981 |
| A hardware logic simulation machine comprised of an array of specially designed parallel processors, with there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork |
| 4291406 |
Error correction on burst channels by sequential decoding |
September 22, 1981 |
| A sequential decoder for error correction on burst and random noise channels using convolutionally encoded data. The decoder interacts with a deinterleaver which time demultiplexes data from a data channel from its time multiplexed form into a predetermined transformed order. The decoder |
