| Patent Number |
Title Of Patent |
Date Issued |
| 7085798 |
Sense-amp based adder with source follower pass gate evaluation tree |
August 1, 2006 |
| A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a differential pass-gate evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby ob |
| 6952113 |
Method of reducing leakage current in sub one volt SOI circuits |
October 4, 2005 |
| A multi-threshold integrated circuit (IC) with reduced subthreshold leakage and method of reducing leakage. Selectable supply switching devices (NFETs and/or PFETs) between a logic circuit and supply connections (V.sub.dd and Ground) for the circuit have higher thresholds than normal cir |
| 6816824 |
Method for statically timing SOI devices and circuits |
November 9, 2004 |
| Low-conductance and high-conductance IV characteristics (models) are created using the low and high end of their body voltage ranges, respectively. The body voltage of the device (FET) is initialized to the low end of range at time zero, and then a transient, two dimensional sweep of |
| 6798682 |
Reduced integrated circuit chip leakage and method of reducing leakage |
September 28, 2004 |
| An integrated circuit that may include an array such as a static random access memory (SRAM) with high threshold device array devices and in selected other devices to reduce leakage. Devices with high threshold have a thicker gate oxide or a high k dielectric gate oxide that is selected |
| 6789099 |
Sense-amp based adder with source follower evaluation tree |
September 7, 2004 |
| A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits |
| 6298467 |
Method and system for reducing hysteresis effect in SOI CMOS circuits |
October 2, 2001 |
| A method for reducing a hysteresis effect in silicon-on-insulator CMOS circuits includes the steps of providing a circuit having CMOS objects, defining a beta ratio; resizing the CMOS objects based on the beta ratio, determining if the objects are a minimum size based on predetermined si |
| 5334886 |
Direct-coupled PNP transistor pull-up ECL circuits and direct-coupled complementary push-pull EC |
August 2, 1994 |
| An emitter coupled logic circuit includes a series connected PNP transistor and diode to improve the pull-up delay and power consumption. The biasing of the PNP transistor is established by utilizing existing voltage levels in the emitter coupled logic circuit with no extra biasing circu |
| 5089724 |
High-speed low-power ECL/NTL circuits with AC-coupled complementary push-pull output stage |
February 18, 1992 |
| High-speed low-power emitter coupled logic (ECL) and non-threshold logic (NTL) circuits are disclosed wherein an ac-coupled complementary push-pull output stage is utilized. The circuits utilize two capacitors to couple an ac-pulse derived from a replica of an input signal to the bases o |
| 5075566 |
Bipolar emitter-coupled logic multiplexer |
December 24, 1991 |
| A high speed multiplexer circuit is described which includes a plurality of input bipolar transistors and a reference bipolar transistor. The input and reference transistors have their emitters commonly coupled to an emitter current supply and their collectors coupled to a collector supp |
| 5003199 |
Emitter coupled logic circuit having an active pull-down output stage |
March 26, 1991 |
| An ECL circuit having an output circuit with improved pull-down characteristics. An active pull-down circuit is provided by a p-channel JFET which includes a back gate connection or a merged p-channel JFET/NPN device. The gate and/or back gate are switched, providing a lowering of th |
| 4864539 |
Radiation hardened bipolar static RAM cell |
September 5, 1989 |
| This invention relates generally to Static Random Access Memory (SRAM) cells and more particularly, relates to a SRAM cell wherein soft-error due to .alpha.-particle radiation is reduced by permitting the potential at the common-emitter node of the cross-coupled transistors of the memory |
