| Patent Number |
Title Of Patent |
Date Issued |
| 6787816 |
Thyristor having one or more doped layers |
September 7, 2004 |
| A method is provided for forming one or more doped layers using ion-implantation in the fabrication of thyristor devices. For example, these thyristors may be made from single crystalline silicon carbide. According to one aspect of the invention, one of the required layers is formed |
| 5510281 |
Method of fabricating a self-aligned DMOS transistor device using SiC and spacers |
April 23, 1996 |
| A method for fabricating a semiconductor device includes patterning a refractory dielectric layer over a semiconductor layer of a first conductivity type; conformally depositing a first spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patternin |
| 4998151 |
Power field effect devices having small cell size and low contact resistance |
March 5, 1991 |
| A multi-cellular power field effect semiconductor device includes a high conductivity layer of metal or a metal silicide disposed in intimate contact with the source region of the device. This high conductivity layer is self-aligned with respect to the aperture in the gate electrode thro |
| 4901127 |
Circuit including a combined insulated gate bipolar transistor/MOSFET |
February 13, 1990 |
| An IGBT and FET are integrated in a common semiconductor body and share common source/emitter, base and drift regions and an insulated gate electrode. The ON-resistance and turn-off time of this device can be controlled by connecting the drain and collector electrodes to one main ter |
| 4862242 |
Semiconductor wafer with an electrically-isolated semiconductor device |
August 29, 1989 |
| A semiconductor wafer having a substrate with an epitaxial layer thereon includes a semiconductor device electrically isolated from the substrate as well as from any other devices in the wafer by electrical isolation structure comprising semiconductor material. The semiconductor device c |
| 4823176 |
Vertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junctio |
April 18, 1989 |
| A power field effect device has a high voltage blocking junction which intersects the device surface under the gate electrode. That intersection is a closed plane geometric figure whose center is within the body region of the device rather than in the more heavily doped base region of th |
| 4801986 |
Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating ar |
January 31, 1989 |
| A power field effect device has a gate grid having a plurality of elongate openings therein through which a base region forming a high voltage blocking junction with the underlying body was diffused. The openings have round ends in order to prevent the formation of spherical portions in |
| 4717679 |
Minimal mask process for fabricating a lateral insulated gate semiconductor device |
January 5, 1988 |
| An eight mask process for forming a lateral insulated gate semiconductor device is disclosed. The gate structure can be used as a mask to align the third and fifth regions of the device and a third protective layer aligns the fourth and sixth regions of the device. |
| 4620211 |
Method of reducing the current gain of an inherent bipolar transistor in an insulated-gate semic |
October 28, 1986 |
| Reduction in the forward current gain of an inherent bipolar transistor in an insulated-gate semiconductor device such as an IGT or an IGFET is achieved by implantation of selected ions into the semiconductor material of such device. The ions, which create defects in the implanted region |
| 4429011 |
Composite conductive structures and method of making same |
January 31, 1984 |
| A composite conductive structure which includes an insulating substrate on which is provided a conductor of molybdenum covered by a layer of molybdenum nitride and a method of making the structure are described. The method includes heating the conductor of molybdenum in an atmosphere of |
| 4333965 |
Method of making integrated circuits |
June 8, 1982 |
| A method of reducing lateral field oxidation in the vicinity of the active regions of a silicon substrate in which integrated circuit elements are to be formed. Mesas, the tops of which are the active regions, are formed by ion beam etching of the silicon substrate. The mesas are protect |
| 4227944 |
Methods of making composite conductive structures in integrated circuits |
October 14, 1980 |
| A method of making a composite conductive structure is described. The structure includes an insulating substrate on which is provided a conductor of a refractory metal substantially nonreactive with silicon dioxide covered by a layer of a silicide of the refractory metal and a layer |
