| Patent Number |
Title Of Patent |
Date Issued |
| 7417896 |
Flash memory device capable of reduced programming time |
August 26, 2008 |
| A flash memory device and related method of operation are provided. The device generally comprises a word line voltage generator circuit configured to generate a word line voltage based on incremental step pulse programming; and a word line voltage controller circuit that controls th |
| 7417895 |
Nor flash memory and erase method thereof |
August 26, 2008 |
| A NOR flash memory includes a plurality of main cells, a plurality of main word lines, a plurality of dummy cells, and a plurality of dummy word lines. The main cells are electrically connected to a bit line and are arranged in a pattern. The main word lines are each electrically con |
| 7379380 |
Low power multi-chip semiconductor memory device and chip enable method thereof |
May 27, 2008 |
| A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual semiconductor chips of the device are activated and deactivated in accordance with internal |
| 7376044 |
Burst read circuit in semiconductor memory device and burst data read method thereof |
May 20, 2008 |
| A semiconductor memory device conducts a burst read operation that avoids interrupt loading on a system. The memory device includes a memory cell array, a sense amplifier, a latch circuit and a burst mode control unit. The sense amplifier is configured to sequentially sense and amplifies |
| 7372738 |
Flash memory device with reduced erase time |
May 13, 2008 |
| A NOR flash memory device comprises a memory cell array, a row selection circuit adapted to drive wordlines in the memory cell array with a wordline voltage during an erase operation, and an erase voltage generating circuit adapted to generate an erase voltage as the wordline voltage |
| 7274598 |
Nonvolatile integrated circuit memory devices having staged application of program voltages and |
September 25, 2007 |
| A nonvolatile integrated circuit memory device includes a memory cell array having a plurality of memory cells. A high voltage generating unit generates first, second, and third program voltages used in programming the memory cell array. A program control unit controls times of applying |
| 7245547 |
Power detector for use in a nonvolatile memory device and method thereof |
July 17, 2007 |
| A nonvolatile memory cell operates without a time delay in an external power mode using an external power source. A power detector includes high voltage generators for generating voltages to a target level in response to a high voltage enable signal. A high voltage level detector detects |
| 7236423 |
Low power multi-chip semiconductor memory device and chip enable method thereof |
June 26, 2007 |
| A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are included. The individual semiconductor chips of the device are activated and deactivated in accordance with internal |
| 6867628 |
Semiconductor memory delay circuit |
March 15, 2005 |
| A circuit includes an input for receiving an input signal, a delay chain connected to the input for delaying the input signal, and a circuit configuration connected to the delay chain downstream of the input, the circuit configuration for supplying a voltage to the delay chain in res |
