| Patent Number |
Title Of Patent |
Date Issued |
| 7445988 |
Trench memory |
November 4, 2008 |
| A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the trench, removal of a p |
| 7445987 |
Offset vertical device |
November 4, 2008 |
| The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first under |
| 7439568 |
Vertical body-contacted SOI transistor |
October 21, 2008 |
| A vertical field effect transistor ("FET") is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator ("SOI") region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator |
| 7439559 |
SOI device with different crystallographic orientations |
October 21, 2008 |
| A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having |
| 7439149 |
Structure and method for forming SOI trench memory with single-sided strap |
October 21, 2008 |
| A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node diel |
| 7439135 |
Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricati |
October 21, 2008 |
| A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top |
| 7439110 |
Strained HOT (hybrid orientation technology) MOSFETs |
October 21, 2008 |
| A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semiconductor layer, (c) a |
| 7436006 |
Hybrid strained orientated substrates and devices |
October 14, 2008 |
| A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material |
| 7427545 |
Trench memory cells with buried isolation collars, and methods of fabricating same |
September 23, 2008 |
| The present invention relates to semiconductor devices, preferably dynamic random access memory (DRAM) cells, each of which contains at least one trench capacitor with a buried isolation collar. The trench capacitor is located in a trench in a semiconductor substrate, and it comprises in |
| 7408229 |
Structure and method for accurate deep trench resistance measurement |
August 5, 2008 |
| A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a deep trench formed within a semiconductor substrate. The deep trench has a dielectric material formed on upper portions of sidewall surfaces thereof, and includes a condu |
| 7388261 |
Structure and method for accurate deep trench resistance measurement |
June 17, 2008 |
| A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a pair of deep trenches formed within a semiconductor substrate. The pair of deep trenches has a dielectric material formed on side and bottom surfaces thereof, and inc |
| 7384842 |
Methods involving silicon-on-insulator trench memory with implanted plate |
June 10, 2008 |
| A method for fabricating silicon-on-insulator (SOI) trench memory includes forming a trench on a substrate, wherein a buried oxide layer is disposed on the substrate, a SOI layer is disposed on the buried oxide layer, and a hardmask layer is disposed on the SOI layer, implanting ions int |
| 7384829 |
Patterned strained semiconductor substrate and device |
June 10, 2008 |
| A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in e |
| 7375413 |
Trench widening without merging |
May 20, 2008 |
| A semiconductor fabrication method comprises steps of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side |
| 7375034 |
Recessing trench to target depth using feed forward data |
May 20, 2008 |
| Recessing a trench using feed forward data is disclosed. In one embodiment, a method includes providing a region on a wafer including a trench area that includes a trench and a field area that is free of any trench, and a material applied over the region so as to fill the trench in t |
| 7358586 |
Silicon-on-insulator wafer having reentrant shape dielectric trenches |
April 15, 2008 |
| A bonded SOI wafer and a method for forming a bonded SOI wafer are provided. According to the disclosed method, a first semiconductor wafer is provided, having a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches exten |
| 7348252 |
Method of forming silicon-on-insulator wafer having reentrant shape dielectric trenches |
March 25, 2008 |
| A method for forming a bonded SOI wafer is provided in which a first wafer having a single-crystal semiconductor region has a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches extending from the outer surface inwardly int |
| 7326986 |
Trench memory |
February 5, 2008 |
| A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the trench, removal of a p |
| 7319259 |
Structure and method for accurate deep trench resistance measurement |
January 15, 2008 |
| A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a pair of deep trenches formed within a semiconductor substrate. The pair of deep trenches has a dielectric material formed on side and bottom surfaces thereof, and inc |
| 7294543 |
DRAM (Dynamic Random Access Memory) cells |
November 13, 2007 |
| A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrap |
| 7288804 |
Electrically programmable .pi.-shaped fuse structures and methods of fabrication thereof |
October 30, 2007 |
| Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and |
| 7264982 |
Trench photodetector |
September 4, 2007 |
| Trench type PIN photodetectors are formed by etching two sets of trenches simultaneously in a semiconductor substrate, the wide trenches having a width more than twice as great as the narrow trenches by a process margin; conformally filling both types of trenches with a sacrificial m |
| 7256439 |
Trench capacitor array having well contacting merged plate |
August 14, 2007 |
| According to an aspect of the invention, a structure is provided in which an array of trench capacitors includes a well contact to a merged buried plate diffusion region. The array, which is disposed in a substrate, includes a contact for receiving a reference potential. Each trench |
| 7247905 |
Offset vertical device |
July 24, 2007 |
| The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first under |
| 7247536 |
Vertical DRAM device with self-aligned upper trench shaping |
July 24, 2007 |
| A method and structure for a memory storage cell in a semiconductor substrate includes forming a dopant source material over a lower portion of a deep trench formed in the substrate. An upper portion of the trench is shaped to a generally rectangular configuration, and the dopant source |
| 7229877 |
Trench capacitor with hybrid surface orientation substrate |
June 12, 2007 |
| Methods of forming a deep trench capacitor memory device and logic devices on a single chip with hybrid surface orientation. The methods allow for fabrication of a system-on-chip (SoC) with enhanced performance including n-type complementary metal oxide semiconductor (CMOS) device SOI ar |
| 7223669 |
Structure and method for collar self-aligned to buried plate |
May 29, 2007 |
| A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench. |
| 7223653 |
Process for forming a buried plate |
May 29, 2007 |
| A method is provided for making a buried plate region in a semiconductor substrate. According to such method, a trench is formed in a semiconductor substrate, the trench having a trench sidewall, the sidewall including an upper portion, and a lower portion disposed below the upper po |
| 7211474 |
SOI device with body contact self-aligned to gate |
May 1, 2007 |
| A region of a semiconductor wafer is converted to an SOI structure by etching a set of isolation trenches for each transistor active area and oxidizing the sidewalls of the trenches to a depth that leaves a pillar of semiconductor that forms a body contact extending from the active area |
| 7170126 |
Structure of vertical strained silicon devices |
January 30, 2007 |
| A trench capacitor vertical-transistor DRAM cell in a SiGe wafer compensates for overhang of the pad nitride by forming an epitaxial strained silicon layer on the trench walls that improves transistor mobility, removes voids from the poly trench fill and reduces resistance on the bit |
| 7153738 |
Method for making a trench memory cell |
December 26, 2006 |
| A process is provided for forming a trench capacitor, such as used in a DRAM memory cell, in which the required number of polysilicon deposition steps and planarization steps are reduced. A first region of a first material is formed in the bottom portion of the trench, and a dielectric |
| 7138308 |
Replacement gate with TERA cap |
November 21, 2006 |
| A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photol |
| 7132324 |
SOI device with different crystallographic orientations |
November 7, 2006 |
| A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having |
| 7129129 |
Vertical device with optimal trench shape |
October 31, 2006 |
| A method of forming a trench in a semiconductor substrate includes a step of converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. |
| 7115934 |
Method and structure for enhancing trench capacitance |
October 3, 2006 |
| A trench capacitor formed with a bottle etch step has a polygonal cross section produced by forming thermally oxidizing the trench walls with thinner oxide at the corners of the trench, then performing the bottle etch step with the nitride in place, thereby extending the trench walls |
| 7084449 |
Microelectronic element having trench capacitors with different capacitance values |
August 1, 2006 |
| A microelectronic element is provided having a major surface, the microelectronic element including a first capacitor formed on a sidewall of a first trench, the first trench being elongated in a downwardly extending direction from the major surface. The microelectronic element furth |
| 7029964 |
Method of manufacturing a strained silicon on a SiGe on SOI substrate |
April 18, 2006 |
| A semiconductor device with an undercut relaxed SiGe layer having voids beneath the SiGe layer. The voids may be filled with a dielectric such as SiO.sub.2. A strained Si layer may be epitaxially grown on the relaxed SiGe layer to combine the benefits of a defect-free strained Si surface |
| 7022622 |
Method and structure to improve properties of tunable antireflective coatings |
April 4, 2006 |
| A method for improving the properties of tunable etch resistant anti-reflective coatings (TERA) is disclosed. The method includes annealing the deposited layer of TERA in an environment containing at least one of hydrogen and deuterium. The annealed layer has an increased concentrati |
| 6974991 |
DRAM cell with buried collar and self-aligned buried strap |
December 13, 2005 |
| In a DRAM cell having a trench, a cell capacitor and a cell transistor, a node conducting element connects the cell capacitor to the cell transistor and a collar is disposed about the node conducting element. The collar is disposed in the substrate at least partially, up to entirely outs |
| 6969648 |
Method for forming buried plate of trench capacitor |
November 29, 2005 |
| A method for forming a buried plate in a trench capacitor is disclosed. The trench is completely filled with a dopant source material such as ASG. The dopant source material is then recessed and the collar material is deposited to form the collar in the upper portion of the trench. After |
| 6967136 |
Method and structure for improved trench processing |
November 22, 2005 |
| A method is provided for making a trench capacitor by forming a trench in a substrate. The trench is then widened and a sacrificial collar is formed on sidewalls of the widened trench. The trench is then vertically deepened to extend below the sidewalls of the sacrificial collar. Subsequ |
| 6943409 |
Trench optical device |
September 13, 2005 |
| A semiconductor device is formed in on a semiconductor substrate starting with a first step, which is to form a wide trench and a narrow trench in the substrate. Then form a first electrode in the narrow trench by depositing a first fill material of a first conductivity type over the |
| 6913968 |
Method and structure for vertical DRAM devices with self-aligned upper trench shaping |
July 5, 2005 |
| A method and structure for a memory storage cell in a semiconductor substrate includes forming a dopant source material over a lower portion of a deep trench formed in the substrate. An upper portion of the trench is shaped to a generally rectangular configuration, and the dopant source |
| 6884715 |
Method for forming a self-aligned contact with a silicide or damascene conductor and the structu |
April 26, 2005 |
| A method of forming a device including a conductor and a contact over a semiconductor substrate starts by depositing first dielectric and first hard mask layers on the substrate. Form a conductor slot through the hard mask and down into or through the first dielectric layer. Form a reces |
| 6806138 |
Integration scheme for enhancing capacitance of trench capacitors |
October 19, 2004 |
| The capacitance of deep trench capacitors is enhanced by increasing the surface area of the doped region of the trench to be used for one electrode of the capacitor. After formation of the deep trench and a collar on an upper region of the trench, and after optional bottling of the t |
