| Patent Number |
Title Of Patent |
Date Issued |
| 7427538 |
Semiconductor on insulator apparatus and method |
September 23, 2008 |
| A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the i |
| 7422971 |
Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made there |
September 9, 2008 |
| The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and t |
| 7420254 |
Semiconductor device having a metal gate electrode |
September 2, 2008 |
| A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, and forming an impurity containing metal layer on the dielectric layer. A metal gate electrode is then formed from the impurity containing metal layer. Also descr |
| 7348284 |
Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
March 25, 2008 |
| A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si.sub.1-x Ge.sub.x layer is formed on the silicon-on-isolator (SOI) substra |
| 7342277 |
Transistor for non volatile memory devices having a carbon nanotube channel and electrically flo |
March 11, 2008 |
| A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or |
| 7268058 |
Tri-gate transistors and methods to fabricate same |
September 11, 2007 |
| Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is |
| 7223679 |
Transistor gate electrode having conductor material layer |
May 29, 2007 |
| Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work |
| 7193279 |
Non-planar MOS structure with a strained channel region |
March 20, 2007 |
| An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switc |
| 7166505 |
Method for making a semiconductor device having a high-k gate dielectric |
January 23, 2007 |
| A method for making a semiconductor device is described. That method includes forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a |
| 7145246 |
Method of fabricating an ultra-narrow channel semiconductor device |
December 5, 2006 |
| A method of forming a nanowire is disclosed. A nanowire having a first dimension is deposited on a first dielectric layer that is formed on a substrate. A sacrificial gate stack having a sacrificial dielectric layer and a sacrificial gate electrode layer is deposited over a first region |
| 7071064 |
U-gate transistors and methods of fabrication |
July 4, 2006 |
| A process is described for manufacturing of non-planar multi-corner transistor structures. A fin of a semiconductor material having a mask on a top surface of the fin is formed on a first insulating layer. A second insulating layer is formed on the fin exposing a top surface of the mask, |
| 7045073 |
Pre-etch implantation damage for the removal of thin film layers |
May 16, 2006 |
| A method for anisotropically and selectively removing a dielectric thin film layer from a substrate layer is disclosed, wherein the dielectric layer is subjected to ion implantation prior to wet etching. This method may be applied adjacent to a structure such as a gate electrode within a |
| 6998686 |
Metal-gate electrode for CMOS transistor applications |
February 14, 2006 |
| Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metal |
| 6974733 |
Double-gate transistor with enhanced carrier mobility |
December 13, 2005 |
| There is disclosed an apparatus including a straining substrate, a device over the substrate including a channel, wherein the straining substrate strains the device in a direction substantially perpendicular to a direction of current flow in the channel. |
| 6900481 |
Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect tran |
May 31, 2005 |
| A method for forming a transistor includes forming a gate dielectric layer over a portion of a semiconductor substrate, the substrate being substantially free of silicon; defining a gate electrode over a portion of the gate dielectric layer; and introducing ions into the substrate pr |
| 6897098 |
Method of fabricating an ultra-narrow channel semiconductor device |
May 24, 2005 |
| A method of forming a nanowire is disclosed. A nanowire having a first dimension is deposited on a first dielectric layer that is formed on a substrate. A sacrificial gate stack having a sacrificial dielectric layer and a sacrificial gate electrode layer is deposited over a first region |
| 6890807 |
Method for making a semiconductor device having a metal gate electrode |
May 10, 2005 |
| A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, and forming an impurity containing metal layer on the dielectric layer. A metal gate electrode is then formed from the impurity containing metal layer. Also descr |
| 6809017 |
Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication |
October 26, 2004 |
| Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-free gate electrode is conductive. |
| 6696345 |
Metal-gate electrode for CMOS transistor applications |
February 24, 2004 |
| Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metal |
| 6667251 |
Plasma nitridation for reduced leakage gate dielectric layers |
December 23, 2003 |
| A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes nitridizing a thin silicon oxide film in a low power, direct plasma formed from nitrogen. A gas having a lower ionization energy than nitrogen, such as for example, helium, may be |
| 6620713 |
Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication |
September 16, 2003 |
| Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-free gate electrode is conductive. |
| 6617210 |
Method for making a semiconductor device having a high-k gate dielectric |
September 9, 2003 |
| A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. An insulating layer, which is compatible with the dielectric layer and |
| 6617209 |
Method for making a semiconductor device having a high-k gate dielectric |
September 9, 2003 |
| A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a g |
| 6610615 |
Plasma nitridation for reduced leakage gate dielectric layers |
August 26, 2003 |
| A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes nitridizing a thin silicon oxide film in a low power, direct plasma formed from nitrogen. A gas having a lower ionization energy than nitrogen, such as for example, helium, may be |
| 6514879 |
Method and apparatus for dry/catalytic-wet steam oxidation of silicon |
February 4, 2003 |
| A configuration of various chemical compound generators coupled to a furnace provides the environment for formation of extremely thin oxides of silicon on a wafer. Dichloroethylene is reacted with oxygen in a first heated reaction chamber and reaction products therefrom are diluted with |
| 5856697 |
Integrated dual layer emitter mask and emitter trench for BiCMOS processes |
January 5, 1999 |
| A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is d |
| 5488003 |
Method of making emitter trench BiCMOS using integrated dual layer emitter mask |
January 30, 1996 |
| A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is d |
