A reconfigurable processor circuit (200) consistent with certain embodiments of the present invention has an array of configurable circuit blocks (208), wherein certain of the configurable circuit blocks (208) comprise one of configurable arithmetic logic units and clocked digital lo
A programmable skew clock signal generator has a frequency generator circuit (104) consistent with the invention produces an output signal F.sub..phi.0 from a reference signal F.sub.ref A frequency accumulator (132, 152) is preloaded with a preload value P.sub.K1 and receives one ref
A distributed amplifier consistent with certain embodiments of the present invention has a plurality of amplifier sections 1 through N (302, 306) with each amplifier section having an input and an output. A plurality of N input transmission line sections are connected in series, with inp